In this part of the tutorial, you will start with the Aes module you created in RTL Module: Aes. You will add RTL logics, then pack them into Vivado IP and Vitis kernel (XO) file. This XO file can be used directly in the Vitis v++ flow to build the XCLBIN overlay files, and you can use the XRT library to realize the kernel control and data transfer between the host and the kernel.