x1 Design Results - x1 Design Results - 2024.1 English - XD100

Vitis Tutorials: AI Engine

Document_ID: XD100
Release_Date: 2024-10-30
Version: 2024.1 English

Vitis Tutorials: AI Engine
AI Engine for Machine Learning Development
Feature Tutorials
A to Z Bare-metal Flow
Using GMIO with AIE
Runtime Parameter Reconfiguration
Packet Switching
Versal Integration for Hardware Emulation and Hardware
AIE-ML Performance Analysis
AIE Compiler Features
Performance Validation in Analysis View
Design Tutorials
AI Engine-ML Programming
AI Engine-ML Architecture
Tiling Parameters Programming
Compute Optimization
Performance Table
Prime Factor FFT-1008 on AIE-ML
AIE-ML LeNet Tutorial
AIE API based FFT for Many Instances Applications on AIE-ML
Softmax Function on AIE-ML
Migrating Farrow Filter from AIE to AIE-ML
AI Engine Development
Feature Tutorials
AI Engine A-to-Z Flow for Linux
AI Engine GMIO Performance Profile
A to Z Bare-metal Flow
Custom Base Platform Creation
AIE Application Creation
PL Application Creation
PS Application Creation
Using GMIO with AIE
AI Engine GMIO Performance Profile
AI Engine GMIO Programming Model
Runtime Parameter Reconfiguration
Packet Switching
Packet Stream Based AI Engine Kernels
Buffer-Based AI Engine Kernels
Buffer-Based AI Engine Kernels with Mixed Data Types
Versal Integration for Hardware Emulation and Hardware
Versal Integration for Hardware Emulation and Hardware
Versal System Design Clocking
Using Floating-Point in the AI Engine
DSP Library
Debug Walkthrough
Porting a Command Line Project to the Vitis IDE Project
X86 Simulation Debug Walkthrough
AI Engine Simulation Debug Walkthrough
Software-Emulation Debug Walkthrough
Hardware-Emulation Debug Walkthrough
Hardware Debug Walkthrough
Design Execution and System Metrics
System Profiling
PL Kernel Analysis
AI Engine Event Trace and Analysis
AI Engine DSP Library and Model Composer
Versal Emulation Waveform Analysis
AXIS External Traffic Generator
AI Engine Performance and Deadlock Analysis Tutorial
AI Engine Graph Execution and Measurement
AI Engine Deadlock Analysis
AI Engine Status Analysis
Implementing an IIR Filter on the AI Engine
Part1a
Part1b
Part2a
Part2b
Post-Link Recompile of an AI Engine Application
Lab 1: Direct AI Engine Recompile Makefile Flow
Lab 2: Vitis Makefile Flow
Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows
Run Traffic Generators with AI Engine Simulation
Run External Traffic Generators with Emulation Flow
Using RTL IP with AI Engines
Using Verilog Traffic Generators in AIE Simulation
AI Engine Compiler Features
Conditional Objects Instantiation
Multirate AI Engine Graphs
Data Multicasting
Two Tone Filter on AIE Using DSP libraries and Vitis Model Composer
Performance Validation in Analysis View of the Vitis Unified IDE
RTL / AI Engine Interfacing Examples
Design Tutorials
Versal Custom Thin Platform Extensible System
AI Engine Datamover Examples
Object oriented C++ template class kernels with AI Engine API style
Description of the AIE kernels - C function style kernels (unused in graph)
Short description of vector datamover optimizations
Special note on preparing the loop
Compile and build AIE design
Simulating and checking the AIE kernels
References
AI Engine Documentation
Vitis Unified Software Development Platform 2021.2 Documentation
Revision History
LeNet
Super Sampling Rate FIR Filters
Single-Kernel FIR Filter Implementation
Multi-Kernel FIR Filter Implementation
Single-Stream Interface
Super Sampling Rate FIR Filter with Dual-Stream Input
Beamforming
Module 01: Custom Platform
Module 02: AI Engine Design
Module 03: PL Design
Module 04: AI Engine and PL Integration
Module 05: Bare-Metal PS Host Application
Module 06: System Integration: Bare Metal
Module 07: PetaLinux
Module 07: PetaLinux boot
Module 08: Linux SW Application
Module 09: System Integration: Linux
Polyphase Channelizer
Prime Factor FFT
2D-FFT
AIE
HLS
FIR Filter
AIE
HLS
N-Body Simulator
Running the Simulation
Build the Design
Building the Design
Full System Design
Host Software
SD Card Image Generation and Hardware Run
Results
x10 Design Results
x1 Design Results
Digital Down-conversion Chain: Converting from Intrinsics to API
FIR Filter
AIE
HLS
Bilinear Interpolation
64K IFFT Using 2D Architecture
Implementing FFT and DFT Designs on AI Engines
Bitonic SIMD Sorting on AI Engine for float Datatypes
Fractional Delay Farrow Filter
1 Million Point float FFT @ 32 Gsps on AI Engine
System Partitioning of a Hough Transform on AI Engine
MUSIC Algorithm
Softmax Function

alt text

Back to home page