Using Verilog Traffic Generators in AIE Simulation - 2024.1 English - XD100

Table of Contents

• Introduction

• Objectives

• Documentation

• Tutorial Overview

• Support

• License

Introduction

Versal™ adaptive SoCs combine programmable logic (PL), processing system (PS), and AI Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. A host of tools, software, libraries, IP, middleware, and frameworks enable Versal adaptive SoCs to support all industry-standard design flows.

Objectives

After completing this tutorial, you should be able to:

• Use Verilog or System Verilog modules to drive traffic in and out of an ADF graph running in the AIE Simulator.

• Create a setup for Verilog/SV based traffic generator running with AIEsim or x86sim process.

• Integrate your own RTL running in external process with AIEsim or x86sim process.

• Run the external Verilog/System Verilog based traffic generator with XSIM as well as other third party simulators.

• Use python-based automation to generate AMD Vivado™ Design Suite TCL scripts and aie instantiable module for your external testbench.

*Note: Note: External Traffic Generators provides only the PL stream traffic injection and recording capabilities for AI Engine Simulation without any expectation of Cycle Accuracy or Cycle Locked simulation.

IMPORTANT: Before beginning the tutorial make sure you have installed the Vitis 2024.1 software. The Vitis release includes all the embedded base platforms including the VCK190 base platform that is used in this tutorial. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from this link: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms/2024.1.html. The common image package contains a prebuilt Linux kernel and root file system that can be used with the Versal board for embedded design development using Vitis.

Before starting this tutorial run the following steps:

1. Go to the directory where you have unzipped the Versal Common Image package.

2. In a Bash shell run the /Common Images Dir/xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linux script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run the /Common Images Dir/xilinx-versal-common-v2024.1/sdk.sh.

3. Set up your ROOTFS, and IMAGE to point to the rootfs.ext4 and Image files located in the /Common Images Dir/xilinx-versal-common-v2024.1 directory.

4. Set up your PLATFORM_REPO_PATHS environment variable to $XILINX_VITIS/lin64/Vitis/2024.1/base_platforms/.

This tutorial targets VCK190 production board for 2024.1 version.

Documentation

Tutorial Overview

Section 1: Overview of the design that will be used in this tutorial.

Section 2: How to integrate external RTL (Verilog/SV) based traffic generator with AIE.

Section 3: Launch the external process with AIEsim process.

Section 4: External RTL simulation in XSIM and other third party simulator support.

Section 5: More on Traffic Generators.

Section 1: Overview of the Design that Will be Used in this Tutorial

The following figure gives an overview of how the data will flow through this example design.

The following table gives a brief overview of all the functionalities involved.

There are two AIE kernels communicating with the user RTL block. The AIE kernels have four PLIOs, two being file I/Os i.e., in_interpolator and out_classifier and the other two being external I/Os i.e., out_interpolator and in_classifier responsible for propagating traffic in/out of the AIE kernels from the external process running the user RTL block.

19-aie_external_io_sv
|- images
|- data
|- user_rtl
|-aie
|  - kernels
|-my_top.v

Section 2: How to Integrate External RTL (Verilog/SV) Based Traffic Generator with AIE

To establish the connection between the RTL and the AIE kernel’s external PLIOs, the XTLM_IPC SystemC modules are required for the interface between an RTL and AIE kernel and these stubs are present inside external aie wrapper stub module which includes all the XTLM IPC modules and needs to be instantiated in the external testbench to establish the connection as mentioned in the following figure. The axi_stream connections from the RTL kernel are made to the stub which transfers the data to AIE kernel and vice versa as seen in following figure.

pl_in0 = adf::input_plio::create("in_classifier",adf::plio_32_bits);
out0 = adf::output_plio::create("out_interpolator",adf::plio_32_bits);

source vivado/vitis
vivado -mode batch -source aie_wrapper_ext_tb_proj.tcl

Section 3: Launch the external process with AIEsim process

After completing section 2, once required scripts are generated, you can launch the external process as follows:

• If already inside the Vivado project, once the project hierarchy is updated after adding the required sources as mentioned in section 2, you can run the simulation as folows:

Parallelly, you can run the aiesimulator on your Linux terminal using the following command.

aiesimulator --pkg-dir Work --profile

Once both external process and AIEsim process are launched, you can start seeing traffic propagating to and from the user RTL as per the following waveform:

• If outside the Vivado project, once the export_sim directory is generated with required simulation scripts, you can traverse inside XSIM directory and run <top_module_name>.sh script to launch the RTL simulation. Also, parallelly launch the AIEsimulator process as already mentioned. The name of the simulator script is based on the name of the top module which is aie_wrapper in this tutorial. The <top_module_name>.sh script is generated for every simulator that can be used to launch the simulation process. You can find the simulator scripts generated in below path.

  export_sim/xsim/<top_module_name>.sh
  

Update aie_wrapper.sh script line no. 72 to launch XSIM in GUI mode by adding --gui flag.

Go inside the desired simulator directory and trigger the simulator script (aie_wrapper.sh) to launch the simulation.

Also, update the generated cmd.tcl file (line no. 11) to run the simulation for desired timestamp or run all so that traffic can be analyzed. You can manually terminate the simulation once traffic is seen propagating between PL-AIE and you have analyzed the same.

When simulation is launched, you can see the traffic propagating to and from the user RTL.

Section 4: External RTL simulation in XSIM and Other Third Party Simulator Support

The external RTL simulation is supported for XSIM and all other third party simulators. You can find the respective simulator scripts generated inside the export_sim directory as per the following directory structure.

export_sim/<simulator_name>/<top_module_name>.sh

Once you finish to analyze the traffic from PL to AIE and AIE to PL, the AIE simulator and RTL simulation should be manually terminated. No Pass/Fail check is done.

Section 5: More on Traffic Generators

This tutorial talks about Verilog/SV based traffic generators and users can also try C-based/Python based traffic generators with AIE. For more details, please refer the tutorial 16-external-traffic-generator-aie

You can also integrate traffic generators with AIE flows i.e., AIEsim/x86sim or emulation flows i.e., SW emulation or HW emulation. For more details, refer Adding-Traffic-Generators-to-Your-Design.

Summary

In this tutorial, you learned how to drive traffic from external Verilog/System-Verilog traffic generators/testbenches to the AIE simulator. For the same, you need to make the appropriate port connections between the AIE kernels, the aie wrapper stubs (for internally connecting XTLM IPC stubs) and the RTL kernel.

To read more about the use of Vitis in the AI Engine flow, see Versal Adaptive SoC AI Engine Programming Environment Chapter 14: Generating Traffic for Simulation and Emulation (UG1076).

• Note - Supported simulators are Xsim and all the third party simulators (Questa/Riviera/Xcelium/VCS).

• Note - You must provide the simulator installer path, gcc path and clibs path in aie_wrapper_ext_tb_proj.tcl script based on the choice of third party simulator.

Support

GitHub issues will be used for tracking requests and bugs. For questions, go to forums.xilinx.com.

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