Step 6: Copying Routing to Other Nets - 2023.2 English

Vivado Design Suite Tutorial: Implementation (UG986)

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2023.2 English
To apply the same fixed route used for net wbOutputData_OBUF[14] to the even index nets, and the fixed route for wbOutputData_OBUF[15] to the odd index nets, use Tcl For loops as described in the following steps.
  1. Select the Tcl Console tab.
  2. Set a Tcl variable to store the route path for the even nets and the odd nets:
    set even [get_property FIXED_ROUTE [get_nets wbOutputData_OBUF[14]]]
    set odd [get_property FIXED_ROUTE [get_nets wbOutputData_OBUF[15]]]
  3. Set a Tcl variable to store the list of nets to be routed, containing all high bit nets of the output data bus, wbOutputData_OBUF[16:31]:
    for {set i 16} {$i<32} {incr i}  {
       lappend routeNets [get_nets wbOutputData_OBUF[$i]]
  4. Unroute the specified nets:
    route_design -unroute -nets $routeNets
  5. Apply the FIXED_ROUTE property of net wbOutputData_OBUF[14] to the even nets:
    for {set i 16} {$i<32} {incr i 2}  {
       set_property FIXED_ROUTE $even [get_nets wbOutputData_OBUF[$i]]
  6. Apply the FIXED_ROUTE property of net wbOutputData_OBUF[15] to the odd nets:
    for {set i 17} {$i<32} {incr i 2}  {
       set_property FIXED_ROUTE $odd [get_nets wbOutputData_OBUF[$i]]

    The even and odd nets of the output data bus, as needed, now have the same routing paths, adding delay to the high order bits. Run the route status report and the datasheet report to validate that the design is as expected.

  7. In the Tcl Console, type the following command:
    Tip: Some routing errors might be reported if the routed design included nets that use some of the nodes you have assigned to the FIXED_ROUTE properties of the manually routed nets. Remember that you enabled Allow Overlap with Unfixed Nets in the Routing Assignment window.
  8. If any routing errors are reported, type the route_design command in the Tcl Console.

    The nets with the FIXED_ROUTE property takes precedence over the auto-routed nets.

  9. After route_design, repeat the report_route_status command to see the clean report.
  10. Examine the output data bus in the Device window, as seen in the following figure:
    • All nets from the output registers to the output pins for the upper bits 14-31 of the output bus wbOutputData have identical fixed routing sections (shown as dashed lines).
    • You need not fix the LOC and the BEL for the output registers. The place_cell command did it in an earlier step.

    Having routed all the upper bit nets, wbOutputData_OBUF[31:14], with the detour needed for added delay, you can now re-examine the timing of output bus.

  11. Select the Timing window.

    Notice the information message in the banner of the window indicating that the report is out of date because timing data has been modified.

  12. Click rerun to update the report with the latest timing information.
  13. Select the Max/Min Delays for Groups > Clocked by wbClk > wbOutputData[0] section to display the timing information for the wbOutputData bus.

    The clock-to-out timing within all bits of output bus wbOutputData is now closely matched to within 83 ps.

  14. Save the constraints to write them to the target XDC, so that they apply every time you compile the design.
  15. Select File > Constraints > Save to save the placement constraints to the target constraint file, bft_full.xdc, in the active constraint set, constrs_1.

    The synthesis and implementation go out-of-date because the constraints were updated. You can force the design to update by clicking on Details in the toolbar because new constraints are already applied.