In this step, make minor changes to the
RTL design sources. These changes necessitate resynthesizing the netlist and
re-implementing the design.
- In the Hierarchy tab of the Sources window, double-click the top-level VHDL
file, core_transform.vhdl under arnd1, to open the file in the Vivado IDE text editor, as shown in the following
figure.
- Go to lines 70 and 71 and make swap the inputs to
uReg
andxReg
. The following code snippet shows the required changes:From To begin process (clk) begin if rising_edge(clk) then xStepReg <= xStep; uReg <= u; xReg <= x; end if; end process;
begin process (clk) begin if rising_edge(clk) then xStepReg <= xStep; --uReg <= u; --xReg <= x; uReg <= x; xReg <= u; end if; end process;
- Save the changes by clicking the Save File
button in the toolbar of the text editor.
As you can see in the following figure, changing the design source files also changes the run status for finished runs from Complete to Out-of-date.