Step 5: Implementing the ECO Changes - 2023.2 English

Vivado Design Suite Tutorial: Implementation (UG986)

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2023.2 English
Before you place and route the updates, check for any illegal logical connections or other logical issues introduced during the ECO that prevent successful implementation of your changes.
  1. In the Vivado ECO Navigator, under Run, click Check ECO.

    The following figure shows the messages generated by the ECO DRC.

    • The two Critical Warnings are due to the partially routed signals that are a result of the ECO and are cleaned up during incremental place and route.
    • The Warning message is due to nets in the debug hub instance that do not drive any loads. This Warning can be ignored.
    • No other warnings were issued and you are ready to implement the changes.

    Because you added additional logic, place the logic using the incremental place, and then route the updated net connections using the incremental route.

  2. In the Vivado ECO Navigator, under Run, click Place Design.

    The Place Design dialog box opens, allowing you to specify additional options for the place_design command. For this exercise, do not specify additional options.

  3. Click OK.

  4. Vivado runs the incremental placer.

    At the end of the place_design step, the incremental Placement Summary is displayed in the Tcl Console.

    The incremental placement summary shows that the following two cells did not have their previous placement reused:

    • The new ECO_LUT3 cell, which had to be placed from scratch.
    • The count_out_reg[7] cell, which had to get updated placement due to the placement of the ECO_LUT3 driving it.
  5. In the Vivado ECO Navigator, under Run, click Route Design.

    The Route Design dialog box opens.

    Depending on your selection, you have four options to route the ECO changes:

    Incremental Route
    This is the default option.
    Route selected pin
    This option limits the route operation to the selected pin.
    Route selected non-Power nets
    This option routes only the selected signal nets.
    Route selected Power nets
    This option routes only the selected VCC/GND nets.

    In this case, the best choice is to route the changes you made incrementally.

  6. Select Incremental Route.
  7. Click OK.

    At the end of the route_design step, the incremental Routing Reuse Summary displays in the Tcl Console.

    Most of the nets did not require any routing and are fully reused.

    Tip: It is a good idea to run report_route_status after the route operation to make sure that all the nets are routed and none of them has any routing issues. This is especially true if you only routed selected pins or selected nets and want to make sure you have not missed any routes.
  8. In the Tcl Console, run the report_route_status command.

    The Design Route Status looks similar to the following status.

    Before you generate a bitstream, run the ECO DRCs on the design.

  9. In the ECO Navigator, click Check ECO. Make sure that no Critical Warnings are generated.

  10. In the Vivado ECO Navigator, under Program, click Save Checkpoint As.

    The Save Checkpoint As dialog box opens. Specify a name for the checkpoint file to write to disk.

  11. Click OK to save a checkpoint file with your changes.

  12. In the Vivado ECO Navigator, under Program, click Generate Bitstream.

    The Generate Bitstream dialog box opens.

    You can specify a name for a Bit file and select the desired options for the write_bitstream operation.

  13. Click OK to generate a bitstream with your changes.

  14. In the Vivado ECO Navigator, under Program, click Write Debug Probes.

    The Write Debug Probes dialog box opens.

    Specify a name for a .ltx file for your debug probes.

  15. Click OK to generate debug probes file (LTX).

    This command allows you to generate a new .ltx file for your debug probes. If you made changes to your debug probes using the Replace Debug Probes command, save the updated information to a new debug probes file to reflect the changes in the Vivado Hardware Manager.

  16. Follow the instructions in Step 3: Validating the Design on the Board to download the generated bitstream programming file and debug probes file into the target FPGA using the Hardware Manager to check your ECO modifications.