Step 1: Creating a Project Using the Vivado New Project Wizard - 2023.2 English

Vivado Design Suite Tutorial: Implementation (UG986)

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2023.2 English
To create a project, use the New Project wizard to name the project, to add RTL source files and constraints, and to specify the target device.
  1. Open the Vivado Design Suite integrated design environment (IDE).
  2. In the Getting Started page, click Create Project to open the New Project wizard.
  3. Click Next.
  4. In the Project Name page, do the following:
    1. Name the new project project_ECO_lab.
    2. Provide the project location C:/Vivado_Tutorial.
    3. Ensure that the Create project subdirectory is selected.
    4. Click Next.
  5. In the Project Type page, do the following:
    1. Specify the type of project to create as RTL Project.
    2. Leave the Do not specify sources at this time check box unchecked.
    3. Click Next.
  6. In the Add Sources page, do the following:
    1. Set the Target Language to Verilog.
    2. Click Add Files.
    3. In the Add Source Files dialog box, navigate to the /src/lab4 directory.
    4. Select all Verilog source files.
    5. Click OK.
    6. Verify that the files are added.
    7. Click Add Files.
    8. In the Add Source Files dialog box, navigate to the /src/lab4/IP directory.
    9. Select all of the XCI source files and click OK.
    10. Verify that the files are added and Copy sources into project is selected.
    11. Click Next.
  7. In the Add Constraints dialog box, do the following:
    1. Click the Add button , and then select Add Files.
    2. Navigate to the /src/lab4 directory and select ECO_kcu105.xdc.
    3. Click Next.
  8. In the Default Part page, do the following:
    1. Select Boards and then select Kintex-UltraScale KCU105 Evaluation Platform.
    2. Click Next.
  9. Review the New Project Summary page. Verify that the data appears as expected, per the steps above.
  10. Click Finish.
    Note: It might take a moment for the project to initialize.
  11. In the Sources window in the Vivado IDE, expand top to see the source files for this lab.