Implementation Tutorial - 2023.2 English

Vivado Design Suite Tutorial: Implementation (UG986)

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2023.2 English
Important: This tutorial requires the use of the AMD Kintex™ 7 and AMD Kintex™ UltraScale™ family of devices. Update your AMD Vivado™ Design Suite tools installation if you do not have these device families installed. Refer to the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for more information on Adding Design Tools or Devices.

This tutorial includes four labs that demonstrate different features of the AMD Vivado Design Suite implementation tool:

  • Lab 1 demonstrates using implementation strategies to meet different design objectives.
  • Lab 2 demonstrates the use of the incremental compile feature after making a small design change.
  • Lab 3 demonstrates the use of manual placement and routing, and duplicated routing, to fine-tune the timing on the design.
  • Lab 4 demonstrates the use of the Vivado ECO to make quick changes to your design post-implementation.

Vivado implementation includes all steps necessary to place and route the netlist onto the FPGA device resources while meeting the logical, physical, and timing constraints of a design.

Video: You can also learn more about implementing the design by viewing the following Quick Take videos:
Training: AMD provides training courses that can help you learn more about the concepts presented in this document. Use these links to explore related courses: