DSP48E1 - 2023.2 English - Primitive: 48-bit Multi-Functional Arithmetic Block

Primitive: 48-bit Multi-Functional Arithmetic Block

Introduction

This design element is a scalable dedicated block in 7 series devices that lets you create compact, high-speed, arithmetic-intensive operations such as those seen for many DSP algorithms. Functions that the block is capable of include multiplication, addition, subtraction, accumulation, shifting, logical operations, and pattern detection.

Port Descriptions

Port	Direction	Width	Function
A<29:0>	Input	30	Data input for pre-adder, multiplier, adder/subtracter/accumulator, ALU, or concatenation operations. When used with the multiplier or pre-adder, 25-bits of data (A[24:0]) is used and upper bits (A[29:25]) are unused and may be tied to ground. When using the internal adder/subtracter/accumulator or ALU circuit, all 30-bits are used (A[29:0]). When used in concatenation mode, all 30-bits are used and this constitutes the MSB (upper) bits of the concatenated vector.
ACIN<29:0>	Input	30	Cascaded data input from ACOUT of previous DSP48E1 slice (multiplexed with A). If not used, tie port to all zeros.
ACOUT<29:0>	Output	30	Cascaded data output to ACIN of next DSP48E1 slice. If not used, leave unconnected.
ALUMODE<3:0>	Input	4	Controls the selection of the logic function in the DSP48E1 slice.
B<17:0>	Input	18	The B input of the multiplier. B[17:0] are the least significant bits (LSBs) of the A:B concatenated input to the second-stage adder/subtracter or logic function.
BCIN<17:0>	Input	18	Cascaded data input from BCOUT of previous DSP48E1 slice (muxed with B). If not used, tie port to all zeros.
BCOUT<17:0>	Output	18	Cascaded data output to BCIN of next DSP48E1 slice. If not used, leave unconnected.
C<47:0>	Input	48	Data input to the second-stage adder/subtracter, pattern detector, or logic function.
CARRYCASCIN	Input	1	Cascaded carry input from CARRYCASCOUT of previous DSP48E1 slice.
CARRYCASCOUT	Output	1	Cascaded carry output to CARRYCASCIN of next DSP48E1 slice. This signal is internally fed back into the CARRYINSEL multiplexer input of the same DSP48E1 slice.
CARRYIN	Input	1	Carry input from the FPGA logic.
CARRYINSEL <2:0>	Input	3	Selects the carry source: 0 1 1 - PCIN[47]: Rounding PCIN (round towards zero) 1 0 0 - CARRYCASCOUT: For larger add/sub/acc (sequential operation via internal feedback). Must select with PREG=1 1 0 1 - ~P[47]: Rounding P (round towards infinity). Must select with PREG=1 1 1 0 - A[24]: XNOR B[17] Rounding A x B 1 1 1 - P[47]: For rounding P (round towards zero). Must select with PREG=1
CARRYOUT<3:0>	Output	4	4-bit carry output from each 12-bit field of the accumulate/adder/logic unit. Normal 48-bit operation uses only CARRYOUT3. SIMD operation can use four carry out bits (CARRYOUT[3:0]).
CEAD	Input	1	Active-High clock enable for the pre-adder output AD pipeline register. Tie to logic one if not used and ADREG=1. Tie to logic zero if ADREG=0.
CEALUMODE	Input	1	Active-High clock enable for ALUMODE (control inputs) registers (ALUMODEREG=1). Tie to logic one if not used.
CEA1	Input	1	Active-High clock enable for the first A (input) register. This port is only used if AREG=2 or INMODE0 = 1. Tie to logic one if not used and AREG=2. Tie to logic zero if AREG=0 or 1. When two registers are used, this is the first sequentially. When Dynamic AB Access is used, this clock enable is applied for INMODE[0]=1.
CEA2	Input	1	Active-High clock enable for the second A (input) register. This port is only used if AREG=1 or 2. Tie to logic one if not used and AREG=1 or 2. Tie to logic zero if AREG=0. When two registers are used, this is the second sequentially. When one register is used (AREG=1), CEA2 is the clock enable.
CEB1	Input	1	Active-High, Clock enable for the first B (input) register. This port is only used if BREG=2 or INMODE4=1. Tie to logic one if not used and BREG=2. Tie to logic zero if BREG=0 or 1. When two registers are used, this is the first sequentially. When Dynamic AB Access is used, this clock enable is applied for INMODE[4]=1.
CEB2	Input	1	Active-High clock enable for the second B (input) register. This port is only used if BREG=1 or 2. Tie to logic one if not used and BREG=1 or 2. Tie to logic zero if BREG=0. When two registers are used, this is the second sequentially. When one register is used (BREG=1), CEB2 is the clock enable.
CEC	Input	1	Active-High clock enable for the C (input) register (CREG=1). Tie to logic one if not used.
CECARRYIN	Input	1	Active-High clock enable for the CARRYIN (input from fabric) register (CARRYINREG=1). Tie to logic one if not used.
CECTRL	Input	1	Active-High clock enable for the OPMODE and CARRYINSEL (control inputs) registers (OPMODEREG=1 or CARRYINSELREG=1). Tie to logic one if not used.
CED	Input	1	Active-High Clock enable for the D (input) registers (DREG=1). Tie to logic one if not used.
CEINMODE	Input	1	Active-High clock enable for the INMODE control input registers (INMODEREG=1). Tie to logic one if not used.
CEM	Input	1	Active-High Clock enable for the post-multiply M (pipeline) register and the internal multiply round CARRYIN register (MREG=1). Tie to logic one if not used.
CEP	Input	1	Active-High clock enable for the P (output) register (PREG=1). Tie to logic one if not used.
CLK	Input	1	The DSP48E1 input clock common to all internal registers and flip-flops.
D<24:0>	Input	25	25-bit data input to the pre-adder or alternative input to the multiplier. The pre-adder implements D + A as determined by the INMODE3 signal.
INMODE<4:0>	Input	5	These five control bits select the functionality of the pre-adder, the A, B, and D inputs, and the input registers. These bits should be tied to all zeros if not used.
MULTSIGNIN	Input	1	Sign of the multiplied result from the previous DSP48E1 slice for MACC extension. Either connect to the MULTSIGNOUT of another DSP block or tie to ground if not used.
MULTSIGNOUT	Output	1	Sign of the multiplied result cascaded to the next DSP48E1 slice for MACC extension. Either connect to the MULTSIGNIN of another DSP block or tie to ground if not used.
OPMODE<6:0>	Input	7	Controls the input to the X, Y, and Z multiplexers in the DSP48E1 slice dictating the operation or function of the DSP slice.
OVERFLOW	Output	1	Active-High Overflow indicator when used with the appropriate setting of the pattern detector and PREG=1.
P<47:0>	Output	48	Data output from second stage adder/subtracter or logic function.
PATTERNBDETECT	Output	1	Active-High match indicator between P[47:0] and the pattern bar.
PATTERNDETECT	Output	1	Active-High Match indicator between P[47:0] and the pattern gated by the MASK. Result arrives on the same cycle as P.
PCIN<47:0>	Input	48	Cascaded data input from PCOUT of previous DSP48E1 slice to adder. If used, connect to PCOUT of upstream cascaded DSP slice. If not used, tie port to all zeros.
PCOUT<47:0>	Output	48	Cascaded data output to PCIN of next DSP48E1 slice. If used, connect to PCIN of downstream cascaded DSP slice. If not used, leave unconnected.
RSTA	Input	1	Active-High synchronous Reset for both A (input) registers (AREG=1 or 2). Tie to logic zero if not used.
RSTALLCARRYIN	Input	1	Active-High, synchronous reset for the Carry (internal path) and the CARRYIN registers (CARRYINREG=1). Tie to logic zero if not used.
RSTALUMODE	Input	1	Active-High synchronous Reset for ALUMODE (control inputs) registers (ALUMODEREG=1). Tie to logic zero if not used.
RSTB	Input	1	Active-High, synchronous Reset for both B (input) registers (BREG=1 or 2). Tie to logic zero if not used.
RSTC	Input	1	Active-High synchronous reset for the C (input) registers (CREG=1). Tie to logic zero if not used.
RSTCTRL	Input	1	Active-High synchronous reset for OPMODE and CARRYINSEL (control inputs) registers (OPMODEREG=1 and/or CARRYINSELREG=1). Tie to logic zero if not used.
RSTD	Input	1	Active-High synchronous reset for the D (input) register and for the pre-adder (output) AD pipeline register (DREG=1 and/or ADREG=1). Tie to logic zero if not used.
RSTINMODE	Input	1	Active-High synchronous reset for the INMODE (control input) registers (INMODEREG=1). Tie to logic zero if not used.
RSTM	Input	1	Active-High synchronous reset for the M (pipeline) registers (MREG=1). Tie to logic zero if not used.
RSTP	Input	1	Active-High, synchronous reset for the P (output) registers (PREG=1). Tie to logic zero if not used.
UNDERFLOW	Output	1	Active-High underflow indicator when used with the appropriate setting of the pattern detector and PREG=1.

Design Entry Method

Instantiation	Yes
Inference	Recommended
IP Catalog	Yes
Macro support	Yes

Available Attributes

Attribute	Type	Allowed Values	Default	Description
ACASCREG	DECIMAL	1, 0, 2	1	In conjunction with AREG, selects the number of A input registers on the A cascade path, ACOUT. This attribute must be equal to or one less than the AREG value: AREG=0: ACASCREG must be 0. AREG=1: ACASCREG must be 1. AREG=2: ACASCREG can be 1 or 2.
ADREG	DECIMAL	1, 0	1	Selects the number of AD pipeline registers. Set to 1 to use the AD pipeline registers.
A_INPUT	STRING	"DIRECT", "CASCADE"	"DIRECT"	Selects the input to the A port between parallel input ("DIRECT") or the cascaded input from the previous slice ("CASCADE").
ALUMODEREG	DECIMAL	1, 0	1	Selects the number of ALUMODE input registers. Set to 1 to register the ALUMODE inputs.
AREG	DECIMAL	1, 0, 2	1	Selects the number of A input pipeline registers.
AUTORESET _PATDET	STRING	"NO_RESET", "RESET_MATCH", "RESET_NOT _MATCH"	"NO_RESET"	Automatically resets the P Register (accumulated value or counter value) on the next clock cycle, if a pattern detect event has occurred on this clock cycle. The "RESET_MATCH" and "RESET_NOT_MATCH" settings distinguish between whether the DSP48E1 slice should cause an auto reset of the P Register on the next cycle: if the pattern is matched or whenever the pattern is not matched on the current cycle but was matched on the previous clock cycle.
BCASCREG	DECIMAL	1, 0, 2	1	In conjunction with BREG, selects the number of B input registers on the B cascade path, BCOUT. This attribute must be equal to or one less than the BREG value: BREG=0: BCASCREG must be 0. BREG=1: BCASCREG must be 1. BREG=2: BCASCREG can be 1 or 2.
B_INPUT	STRING	"DIRECT", "CASCADE"	"DIRECT"	Selects the input to the B port between parallel input ("DIRECT") or the cascaded input from the previous slice ("CASCADE").
BREG	DECIMAL	1, 0, 2	1	Selects the number of B input registers.
CARRYINREG	DECIMAL	1, 0	1	Selects the number of CARRYIN input registers. Set to 1 to register the CARRYIN inputs.
CARRYINSELREG	DECIMAL	1, 0	1	Selects the number of CARRYINSEL input registers. Set to 1 to register the CARRYINSEL inputs.
CREG	DECIMAL	1, 0	1	Selects the number of C input registers. Set to 1 to register the C inputs.
DREG	DECIMAL	1, 0	1	Selects the number of D input registers. Set to 1 to register the D inputs.
INMODEREG	DECIMAL	1, 0	1	Selects the number of INMODE input registers. Set to 1 to register the INMODE inputs.
MASK	HEX	48-bit HEX	All ones	This 48-bit value is used to mask out certain bits during a pattern detection. When a MASK bit is set to 1, the corresponding pattern bit is ignored. When a MASK bit is set to 0, the pattern bit is compared.
MREG	DECIMAL	1, 0	1	Selects the number of multiplier output (M) pipeline register stages. Set to 1 to use the M pipeline registers.
OPMODEREG	DECIMAL	1, 0	1	Selects the number of OPMODE input registers. Set to 1 to register the OPMODE inputs.
PATTERN	HEX	48-bit HEX	All zeros	This 48-bit value is used in the pattern detector.
PREG	DECIMAL	1, 0	1	Selects the number of P output registers. Set to 1 to register the P outputs. The registered outputs will include: CARRYOUT CARRYCASCOUT MULTSIGNOUT PATTERNB_DETECT PCOUT
SEL_MASK	STRING	"MASK", "C", "ROUNDING _MODE1", "ROUNDING _MODE2"	"MASK"	Selects the mask to be used for the pattern detector. The C and MASK settings are for standard uses of the pattern detector (counter, overflow detection, etc.). ROUNDING_MODE1 (Cbar left shifted by 1) and ROUNDING_MODE2 (C-bar left shifted by 2) select special masks based off of the optionally registered C port. These rounding modes can be used to implement convergent rounding in the DSP48E1 slice using the pattern detector.
SEL_PATTERN	STRING	"PATTERN", "C"	"PATTERN"	Selects the input source for the pattern field. The input source can either be a 48-bit dynamic C input or a 48-bit static PATTERN attribute field.
USE_DPORT	BOOLEAN	FALSE, TRUE	FALSE	Determines whether the pre-adder and the D Port are used or not.
USE_MULT	STRING	"MULTIPLY", "DYNAMIC", "NONE"	"MULTIPLY"	Selects usage of the multiplier. Set to "NONE" to save power when using only the Adder/Logic Unit. The "DYNAMIC" setting indicates that the user is switching between A*B and A:B operations on the fly and therefore needs to get the worst-case timing of the two paths.
USE_PATTERN _DETECT	STRING	"NO_PATDET", "PATDET"	"NO_PATDET"	Selects whether the pattern detector and related features are used ("PATDET") or not used ("NO_PATDET"). This attribute is used for speed specification and Simulation Model purposes only.
USE_SIMD	STRING	"ONE48", "FOUR12", "TWO24"	"ONE48"	Selects the mode of operation for the adder/subtracter. The attribute setting can be one 48-bit adder mode ("ONE48"), two 24- bit adder mode ("TWO24"), or four 12-bit adder mode ("FOUR12"). Selecting "ONE48" mode is compatible with Virtex-5 DSP48 operation and is not actually a true SIMD mode. Typical Multiply-Add operations are supported when the mode is set to "ONE48". When either "TWO24" or "FOUR12" mode is selected, the multiplier must not be used, and USE_MULT must be set to "NONE".

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- DSP48E1: 48-bit Multi-Functional Arithmetic Block
--          7 Series
-- Xilinx HDL Language Template, version 2023.2

DSP48E1_inst : DSP48E1
generic map (
   -- Feature Control Attributes: Data Path Selection
   A_INPUT => "DIRECT",               -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
   B_INPUT => "DIRECT",               -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
   USE_DPORT => FALSE,                -- Select D port usage (TRUE or FALSE)
   USE_MULT => "MULTIPLY",            -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
   USE_SIMD => "ONE48",               -- SIMD selection ("ONE48", "TWO24", "FOUR12")
   -- Pattern Detector Attributes: Pattern Detection Configuration
   AUTORESET_PATDET => "NO_RESET",    -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
   MASK => X"3fffffffffff",           -- 48-bit mask value for pattern detect (1=ignore)
   PATTERN => X"000000000000",        -- 48-bit pattern match for pattern detect
   SEL_MASK => "MASK",                -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
   SEL_PATTERN => "PATTERN",          -- Select pattern value ("PATTERN" or "C")
   USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
   -- Register Control Attributes: Pipeline Register Configuration
   ACASCREG => 1,                     -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
   ADREG => 1,                        -- Number of pipeline stages for pre-adder (0 or 1)
   ALUMODEREG => 1,                   -- Number of pipeline stages for ALUMODE (0 or 1)
   AREG => 1,                         -- Number of pipeline stages for A (0, 1 or 2)
   BCASCREG => 1,                     -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
   BREG => 1,                         -- Number of pipeline stages for B (0, 1 or 2)
   CARRYINREG => 1,                   -- Number of pipeline stages for CARRYIN (0 or 1)
   CARRYINSELREG => 1,                -- Number of pipeline stages for CARRYINSEL (0 or 1)
   CREG => 1,                         -- Number of pipeline stages for C (0 or 1)
   DREG => 1,                         -- Number of pipeline stages for D (0 or 1)
   INMODEREG => 1,                    -- Number of pipeline stages for INMODE (0 or 1)
   MREG => 1,                         -- Number of multiplier pipeline stages (0 or 1)
   OPMODEREG => 1,                    -- Number of pipeline stages for OPMODE (0 or 1)
   PREG => 1                          -- Number of pipeline stages for P (0 or 1)
)
port map (
   -- Cascade: 30-bit (each) output: Cascade Ports
   ACOUT => ACOUT,                   -- 30-bit output: A port cascade output
   BCOUT => BCOUT,                   -- 18-bit output: B port cascade output
   CARRYCASCOUT => CARRYCASCOUT,     -- 1-bit output: Cascade carry output
   MULTSIGNOUT => MULTSIGNOUT,       -- 1-bit output: Multiplier sign cascade output
   PCOUT => PCOUT,                   -- 48-bit output: Cascade output
   -- Control: 1-bit (each) output: Control Inputs/Status Bits
   OVERFLOW => OVERFLOW,             -- 1-bit output: Overflow in add/acc output
   PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect output
   PATTERNDETECT => PATTERNDETECT,   -- 1-bit output: Pattern detect output
   UNDERFLOW => UNDERFLOW,           -- 1-bit output: Underflow in add/acc output
   -- Data: 4-bit (each) output: Data Ports
   CARRYOUT => CARRYOUT,             -- 4-bit output: Carry output
   P => P,                           -- 48-bit output: Primary data output
   -- Cascade: 30-bit (each) input: Cascade Ports
   ACIN => ACIN,                     -- 30-bit input: A cascade data input
   BCIN => BCIN,                     -- 18-bit input: B cascade input
   CARRYCASCIN => CARRYCASCIN,       -- 1-bit input: Cascade carry input
   MULTSIGNIN => MULTSIGNIN,         -- 1-bit input: Multiplier sign input
   PCIN => PCIN,                     -- 48-bit input: P cascade input
   -- Control: 4-bit (each) input: Control Inputs/Status Bits
   ALUMODE => ALUMODE,               -- 4-bit input: ALU control input
   CARRYINSEL => CARRYINSEL,         -- 3-bit input: Carry select input
   CLK => CLK,                       -- 1-bit input: Clock input
   INMODE => INMODE,                 -- 5-bit input: INMODE control input
   OPMODE => OPMODE,                 -- 7-bit input: Operation mode input
   -- Data: 30-bit (each) input: Data Ports
   A => A,                           -- 30-bit input: A data input
   B => B,                           -- 18-bit input: B data input
   C => C,                           -- 48-bit input: C data input
   CARRYIN => CARRYIN,               -- 1-bit input: Carry input signal
   D => D,                           -- 25-bit input: D data input
   -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
   CEA1 => CEA1,                     -- 1-bit input: Clock enable input for 1st stage AREG
   CEA2 => CEA2,                     -- 1-bit input: Clock enable input for 2nd stage AREG
   CEAD => CEAD,                     -- 1-bit input: Clock enable input for ADREG
   CEALUMODE => CEALUMODE,           -- 1-bit input: Clock enable input for ALUMODE
   CEB1 => CEB1,                     -- 1-bit input: Clock enable input for 1st stage BREG
   CEB2 => CEB2,                     -- 1-bit input: Clock enable input for 2nd stage BREG
   CEC => CEC,                       -- 1-bit input: Clock enable input for CREG
   CECARRYIN => CECARRYIN,           -- 1-bit input: Clock enable input for CARRYINREG
   CECTRL => CECTRL,                 -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
   CED => CED,                       -- 1-bit input: Clock enable input for DREG
   CEINMODE => CEINMODE,             -- 1-bit input: Clock enable input for INMODEREG
   CEM => CEM,                       -- 1-bit input: Clock enable input for MREG
   CEP => CEP,                       -- 1-bit input: Clock enable input for PREG
   RSTA => RSTA,                     -- 1-bit input: Reset input for AREG
   RSTALLCARRYIN => RSTALLCARRYIN,   -- 1-bit input: Reset input for CARRYINREG
   RSTALUMODE => RSTALUMODE,         -- 1-bit input: Reset input for ALUMODEREG
   RSTB => RSTB,                     -- 1-bit input: Reset input for BREG
   RSTC => RSTC,                     -- 1-bit input: Reset input for CREG
   RSTCTRL => RSTCTRL,               -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
   RSTD => RSTD,                     -- 1-bit input: Reset input for DREG and ADREG
   RSTINMODE => RSTINMODE,           -- 1-bit input: Reset input for INMODEREG
   RSTM => RSTM,                     -- 1-bit input: Reset input for MREG
   RSTP => RSTP                      -- 1-bit input: Reset input for PREG
);

-- End of DSP48E1_inst instantiation

Verilog Instantiation Template


// DSP48E1: 48-bit Multi-Functional Arithmetic Block
//          7 Series
// Xilinx HDL Language Template, version 2023.2

DSP48E1 #(
   // Feature Control Attributes: Data Path Selection
   .A_INPUT("DIRECT"),               // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
   .B_INPUT("DIRECT"),               // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
   .USE_DPORT("FALSE"),              // Select D port usage (TRUE or FALSE)
   .USE_MULT("MULTIPLY"),            // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
   .USE_SIMD("ONE48"),               // SIMD selection ("ONE48", "TWO24", "FOUR12")
   // Pattern Detector Attributes: Pattern Detection Configuration
   .AUTORESET_PATDET("NO_RESET"),    // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
   .MASK(48'h3fffffffffff),          // 48-bit mask value for pattern detect (1=ignore)
   .PATTERN(48'h000000000000),       // 48-bit pattern match for pattern detect
   .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
   .SEL_PATTERN("PATTERN"),          // Select pattern value ("PATTERN" or "C")
   .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
   // Register Control Attributes: Pipeline Register Configuration
   .ACASCREG(1),                     // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
   .ADREG(1),                        // Number of pipeline stages for pre-adder (0 or 1)
   .ALUMODEREG(1),                   // Number of pipeline stages for ALUMODE (0 or 1)
   .AREG(1),                         // Number of pipeline stages for A (0, 1 or 2)
   .BCASCREG(1),                     // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
   .BREG(1),                         // Number of pipeline stages for B (0, 1 or 2)
   .CARRYINREG(1),                   // Number of pipeline stages for CARRYIN (0 or 1)
   .CARRYINSELREG(1),                // Number of pipeline stages for CARRYINSEL (0 or 1)
   .CREG(1),                         // Number of pipeline stages for C (0 or 1)
   .DREG(1),                         // Number of pipeline stages for D (0 or 1)
   .INMODEREG(1),                    // Number of pipeline stages for INMODE (0 or 1)
   .MREG(1),                         // Number of multiplier pipeline stages (0 or 1)
   .OPMODEREG(1),                    // Number of pipeline stages for OPMODE (0 or 1)
   .PREG(1)                          // Number of pipeline stages for P (0 or 1)
)
DSP48E1_inst (
   // Cascade: 30-bit (each) output: Cascade Ports
   .ACOUT(ACOUT),                   // 30-bit output: A port cascade output
   .BCOUT(BCOUT),                   // 18-bit output: B port cascade output
   .CARRYCASCOUT(CARRYCASCOUT),     // 1-bit output: Cascade carry output
   .MULTSIGNOUT(MULTSIGNOUT),       // 1-bit output: Multiplier sign cascade output
   .PCOUT(PCOUT),                   // 48-bit output: Cascade output
   // Control: 1-bit (each) output: Control Inputs/Status Bits
   .OVERFLOW(OVERFLOW),             // 1-bit output: Overflow in add/acc output
   .PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect output
   .PATTERNDETECT(PATTERNDETECT),   // 1-bit output: Pattern detect output
   .UNDERFLOW(UNDERFLOW),           // 1-bit output: Underflow in add/acc output
   // Data: 4-bit (each) output: Data Ports
   .CARRYOUT(CARRYOUT),             // 4-bit output: Carry output
   .P(P),                           // 48-bit output: Primary data output
   // Cascade: 30-bit (each) input: Cascade Ports
   .ACIN(ACIN),                     // 30-bit input: A cascade data input
   .BCIN(BCIN),                     // 18-bit input: B cascade input
   .CARRYCASCIN(CARRYCASCIN),       // 1-bit input: Cascade carry input
   .MULTSIGNIN(MULTSIGNIN),         // 1-bit input: Multiplier sign input
   .PCIN(PCIN),                     // 48-bit input: P cascade input
   // Control: 4-bit (each) input: Control Inputs/Status Bits
   .ALUMODE(ALUMODE),               // 4-bit input: ALU control input
   .CARRYINSEL(CARRYINSEL),         // 3-bit input: Carry select input
   .CLK(CLK),                       // 1-bit input: Clock input
   .INMODE(INMODE),                 // 5-bit input: INMODE control input
   .OPMODE(OPMODE),                 // 7-bit input: Operation mode input
   // Data: 30-bit (each) input: Data Ports
   .A(A),                           // 30-bit input: A data input
   .B(B),                           // 18-bit input: B data input
   .C(C),                           // 48-bit input: C data input
   .CARRYIN(CARRYIN),               // 1-bit input: Carry input signal
   .D(D),                           // 25-bit input: D data input
   // Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
   .CEA1(CEA1),                     // 1-bit input: Clock enable input for 1st stage AREG
   .CEA2(CEA2),                     // 1-bit input: Clock enable input for 2nd stage AREG
   .CEAD(CEAD),                     // 1-bit input: Clock enable input for ADREG
   .CEALUMODE(CEALUMODE),           // 1-bit input: Clock enable input for ALUMODE
   .CEB1(CEB1),                     // 1-bit input: Clock enable input for 1st stage BREG
   .CEB2(CEB2),                     // 1-bit input: Clock enable input for 2nd stage BREG
   .CEC(CEC),                       // 1-bit input: Clock enable input for CREG
   .CECARRYIN(CECARRYIN),           // 1-bit input: Clock enable input for CARRYINREG
   .CECTRL(CECTRL),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
   .CED(CED),                       // 1-bit input: Clock enable input for DREG
   .CEINMODE(CEINMODE),             // 1-bit input: Clock enable input for INMODEREG
   .CEM(CEM),                       // 1-bit input: Clock enable input for MREG
   .CEP(CEP),                       // 1-bit input: Clock enable input for PREG
   .RSTA(RSTA),                     // 1-bit input: Reset input for AREG
   .RSTALLCARRYIN(RSTALLCARRYIN),   // 1-bit input: Reset input for CARRYINREG
   .RSTALUMODE(RSTALUMODE),         // 1-bit input: Reset input for ALUMODEREG
   .RSTB(RSTB),                     // 1-bit input: Reset input for BREG
   .RSTC(RSTC),                     // 1-bit input: Reset input for CREG
   .RSTCTRL(RSTCTRL),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
   .RSTD(RSTD),                     // 1-bit input: Reset input for DREG and ADREG
   .RSTINMODE(RSTINMODE),           // 1-bit input: Reset input for INMODEREG
   .RSTM(RSTM),                     // 1-bit input: Reset input for MREG
   .RSTP(RSTP)                      // 1-bit input: Reset input for PREG
);

// End of DSP48E1_inst instantiation

Related Information

7 Series DSP48E1 Slice User Guide (UG479)

DSP48E1 - 2023.2 English - Primitive: 48-bit Multi-Functional Arithmetic Block - UG953

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)