Using the CLOCK_REGION Property on Clock Buffers - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

You can use the CLOCK_REGION constraint to assign a clock buffer to a clock region without specifying a site. This gives the placer more flexibility when optimizing all the clock trees and when determining the appropriate buffer sites to successfully route all clocks.

You can also use a CLOCK_REGION constraint to provide guidance on the placement of cascaded clock buffers or clock buffers driven by non-clocking primitives, such as fabric logic.

In the following example, the XDC constraint assigns the clkgen/clkout2_buf clock buffer to the CLOCK_REGION X2Y2.

set_property CLOCK_REGION X2Y2 [get_cells clkgen/clkout2_buf]
Note: In most cases, the clock buffers are directly driven by input clock ports, MMCMs, PLLs, or GT*_CHANNELs that are already constrained to a clock region. If this is the case, the clock buffers are automatically placed in the same clock region, and you do not need to use the CLOCK_REGION constraint.