Using SLR Crossing Registers - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

When targeting UltraScale+ SSI technology devices, you can map a register-to-register SLR crossing to a Laguna TX_REG driving a Laguna RX_REG directly. This type of connection is only possible in the UltraScale+ device family, where the Vivado router can fix hold time violations by setting local programmable clock delays. Using the TX_REG to RX_REG SLR crossing topology for pipeline register crossings offers the following performance advantages:

  • The placement of SLR crossings spreads vertically, reducing routing congestion near SLR boundaries.
  • Locating registers in Laguna sites improves delay estimation accuracy, resulting in higher timing QoR.
  • SLR-crossing performance becomes faster and more consistent.
Note: When targeting UltraScale SSI technology devices, you can only use a Laguna TX_REG or RX_REG on a SLR crossing net, and you cannot use both at the same time. Performance advantages are similar to the ones listed above.

You can set the USER_SLL_REG property on registers that you expect to be placed at an SLR crossing boundary on a Laguna register site. The USER_SLL_REG constraint is ignored by place_design if the register D and Q pins are connected to a net that either does not cross an SLR boundary or drives loads placed in multiple SLRs. For example:

set_property USER_SLL_REG TRUE [get_cells {reg_A reg_B}]

A reliable method of mapping registered crossings to Laguna is to apply both BEL and LOC constraints to the registers to lock them in place. The LOC value assigns the Laguna site, and the BEL value chooses a particular Laguna register inside the site, one of six TX_REG registers or one of six RX_REG registers. Laguna crossing registers are a fixed distance apart, which means that each TX_REG register is paired with an RX_REG register for a direct connection.

In the following example, a register-to-register connection is manually placed onto a TX_REG to RX_REG connection. Pipeline register reg_A drives a single fanout with the single load of register reg_B. For a VU9P target device, the following XDC constraints are applied so that reg_A in SLR2 drives reg_B in SLR1 using a direct TX_REG to RX_REG connection:

set_property BEL TX_REG3 [get_cells reg_A]
set_property BEL RX_REG3 [get_cells reg_B]
set_property LOC LAGUNA_X2Y480 [get_cells reg_A]
set_property LOC LAGUNA_X2Y360 [get_cells reg_B]

The BEL assignments are applied first, and the register position (0, 1, ... 5) must match between TX_REG and RX_REG, which is 3 for this example. Finally, the distance between paired Laguna sites is 120 rows. The register reg_A drives from the bottom row of the SLR2 Laguna column across to the bottom row of the SLR1 Laguna column. When creating LAGUNA BEL and LOC constraints, try grouping registers with same clock, clock enable and reset signals to avoid control set compatibility issues.