Timing Exceptions Precedence and Priority Rules - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-11-29
Version
2023.2 English

Timing exceptions are subject to strict precedence and priority rules. The most important rules are as follows:

  • The more specific the constraint, the higher the priority. For example:
    set_max_delay -from [get_clocks clkA] -to [get_pins inst0/D] 12
    set_max_delay -from [get_clocks clkA] -to [get_clocks clkB] 10
    The first set_max_delay constraint has a higher priority because the -to option uses a pin, which is more specific than a clock.
  • The exceptions priority is as follows:
    1. set_false_path
    2. set_max_delay or set_min_delay
    3. set_multicycle_path

The set_clock_groups command is not considered a timing exception even though it is equivalent to two set_false_path commands between two clocks. It has higher precedence than the timing exceptions.

The set_case_analysis and set_disable_timing commands disable timing analysis on specific portions of the design. They have higher precedence than the timing exceptions.

For details on XDC precedence and priorities, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).