Routing (route_design) - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

The Vivado Design Suite router performs routing on the placed design and performs optimization on the routed design to resolve hold time violations. By default, the router performs optimization using a balance between compile time and design operating clock frequency while alleviating congestion. Some router directives sacrifice compile time for better design maximum clock frequency and more aggressive congestion reduction. For more information on routing, see this link in the Vivado Design Suite User Guide: Implementation (UG904).