Resets - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

Resets are one of the more common and important control signals to take into account and limit in your design. Resets can significantly impact your design's maximum clock frequency, area, and power.

Inferred synchronous code might result in resources such as:

  • LUTs
  • Registers
  • SRLs
  • Block or LUT memory
  • DSP48 registers

The choice and use of resets can affect the selection of these components, resulting in less optimal resources for a given design. A misplaced reset on an array can mean the difference between inferring one block RAM, or inferring several thousand registers.

Asynchronous resets described at the input or output of a multiplier might result in registers placed in the slices rather than the DSP block. In such situations, additional logic resources are used, which negatively impacts the power consumption and design performance.