Report Timing from or to the Port - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

Whether a port is already constrained or not, you can use the report_timing command to identify its related clocks in the design. Once all the timing clocks have been defined, you can report the worst path from or to the I/O port, create the I/O delay constraint relative to the clock reported, and rerun the same timing report from/to the other clocks of the design. If it appears that the port is related to more than one clock, create the corresponding constraint and repeat the process.

For example, the din input port is related to the clocks clk1 and clk2 inside the design:

report_timing -from [get_ports din] -sort_by group

The report shows that the din port is related to clk1. The input delay constraint is (for both min and max delay in this example):

set_input_delay -clock clk1 5 [get_ports din]

Rerun timing analysis with the same command as previously, and observe that din is also related to clk2 due to the -sort_by group option, which reports N paths per endpoint clock. You can add the corresponding delay constraint and rerun the report to validate that the din port is not related to another clock.

You can also run the same analysis using the Timing Summary report with the -report_unconstrained option. With only clock constraints in your design, the Unconstrained Paths section appears as follows:

| Unconstrained Path Table
Path Group   From Clock   To Clock   
----------   ----------   --------   
(none)     clk1
(none)     clk2
(none)             clk1
(none)             clk2

The fields without a clock name (or <NONE> in the Vivado IDE) refer to a group of paths where the startpoints (From Clock) or the endpoints (To Clock) are not associated with a clock. The unconstrained I/O ports fall in this category. You can retrieve their name by browsing the rest of the report. For example in the Vivado IDE, by selecting the Setup paths for the clk1 to NONE category, you can see the ports driven by clk1 in the To column:

Figure 1. Getting a List of Unconstrained Output Ports

After adding the new constraints and applying them in memory, you must rerun the report to determine which ports are still unconstrained. For most designs, you must increase the number of reported paths to make sure all the I/O paths are listed in the report.