Path Between Master and Generated Clocks - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

Unlike primary clocks, generated clocks must be defined in the transitive fanout of their master clock, so that the timing engine can accurately compute their insertion delay. Failure to follow this rule will result in improper timing analysis and most likely in invalid slack computation. For example, in the following figure gen_clk_reg/Q is being used as a clock for the next flop (q_reg), and it is also in the fanout cone of the primary clock c1. Hence gen_clk_reg/Q should have a create_generated_clock on it, rather than a create_clock.

Figure 1. Generated Clock in the Fanout Of Master Clock

create_generated_clock -name GC1 -source [get_pins gen_clk_reg/C] -divide_by 2 
[get_pins gen_clk_reg/Q]