PCIE4C to HBM AXI Paths within SLR0 - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

To achieve optimal timing QoR and minimize routing congestion when designing with HBM and PCIE4C, AMD recommends using the PCIE4C sites that are farthest away from the 32 HBM AXI interface in SLR0. In the following figure, these sites are PCIE4CE4_X0Y1 and PCIE4CE4_X1Y1 indicated by the green arrows.

Figure 1. Recommended PCIE4C Sites in SLR0 of a Virtex UltraScale+ HBM vu37p Device