Overlapping Clocks Driven by a Clock Multiplexer - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

When two or more clocks drive into a multiplexer (or more generally a combinatorial cell), they all propagate through and become overlapped on the fanout of the cell. Realistically, only one clock can propagate at a time, but timing analysis allows reporting several timing modes at the same time.

For this reason, you must review the CDC paths and add new constraints to ignore some of the clock relationships. The correct constraints are dictated by how and where the clocks interact in the design.

The following figure shows an example of two clocks driving into a multiplexer and the possible interactions between them before and after the multiplexer.

Figure 1. Multiplexed Clocks

  • Case in which the paths A, B, and C do not exist

    clk0 and clk1 only interact in the fanout of the multiplexer (FDM0 and FDM1). It is safe to apply the clock groups constraint to clk0 and clk1 directly.

    set_clock_groups -logically_exclusive -group clk0 -group clk1
  • Case in which only the paths A or B or C exist

    clk0 and/or clk1 directly interact with the multiplexed clock. To keep timing paths A, B, and C, the constraint cannot be applied to clk0 and clk1 directly. Instead, it must be applied to the portion of the clocks in the fanout of the multiplexer, which requires additional clock definitions.

    create_generated_clock -name clk0mux -divide_by 1 \
    -source [get_pins mux/I0] [get_pins mux/O]
    create_generated_clock -name clk1mux -divide_by 1 \
      -add -master_clock clk1 \
    -source [get_pins mux/I1] [get_pins mux/O]
    set_clock_groups -physically_exclusive -group clk0mux -group clk1mux