Internal VREF and DCI Cascade Constraints - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

Based on the settings for DCI Cascade and Internal VREF, you can free up pins to be used for regular I/Os. These settings also ensure that related DRC checks are run to validate the legality of the constraints. For more information, see either the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the UltraScale Architecture SelectIO Resources User Guide (UG571), depending on your device.