Global Clock Buffer Connectivity and Routing Tracks - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
Release Date
2023.2 English

Each of the 24 BUFGCE buffers in a clock region can only drive a specific clock routing track. However, the BUFGCTRL and BUFGCE_DIV outputs can use any of the 24 tracks by going through a MUX structure. Each BUFGCE_DIV shares the input connectivity with a specific BUFGCE site, and each BUFGCTRL shares input connectivity with two specific BUFGCE sites. Consequently, when BUFGCE_DIV or BUFGCTRL buffers are used in the clock region, use of the BUFGCE buffers is limited. The following figure shows the bottom 6 BUFGCE in a clock region, which are replicated 4 times within a clock region.

Note: A global clock net is assigned to a specific track ID in the device for all the vertical, horizontal routing, and distribution resources the clock uses. A clock cannot change track IDs unless the clock goes through another clock buffer.
Figure 1. BUFGCE, BUFGCE_DIV, and BUFGCTRL Shared Inputs and Output Multiplexing