DRC Closure - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-11-29
Version
2023.2 English

The Vivado Design Suite includes a list of design rule checks (DRCs) you can run using the report_drc Tcl command. The list of DRCs is split among multiple rule decks. During implementation, some of these rule decks are automatically executed as pre-condition DRCs for some commands, such as opt_design, place_design, and route_design.

You must carefully assess the violations from the pre-condition DRCs and from the report_drc command. It is important to review these messages as early as possible to avoid timing or logic-related issues later in the implementation flow. Any Critical Warning DRCs during implementation become Errors during bitstream generation. You must address the Critical Warning and Warning DRCs prior moving to the next implementation stage.

Tip: For DRC violations that can be safely ignored, use the waiver mechanism to waive the violations. For details, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

For more information on the report_drc Tcl command, see the Vivado Design Suite Tcl Command Reference Guide (UG835).