Constraining Clock Domain Crossings - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

Upon verification of the clocking constraints, you must identify asynchronous and over-constrained clock domain crossing paths.

Note: This section does not explain how to properly cross clock region boundaries. Instead, it explains how to identify which crossings exist and how to constrain them.