Clock Tree Topology - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-11-29
Version
2023.2 English

When working with clock trees, follow these recommendations:

  • Run the report_clock_networks command to show the clock network in detail tree view.
  • Utilize clock trees in a way to minimize skew.
  • For the outputs of PLLs and MMCMs, use the same clock buffer type to minimize skew.
  • Look for unintended cascaded BUFG elements that can introduce additional delay, skew, or both.