Clock Latency at the Source - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

It is possible to model the latency of a clock at its source by using the set_clock_latency command with the -source option. This is useful in two cases:

  • To specify the clock delay propagation outside the device independently from the input and output delay constraints.
  • To model the internal propagation latency of a clock used by a block during out-of-context compilation. In such a compilation flow, the complete clock tree is not described, so the variation between min and max operating conditions outside the block cannot be automatically computed and must be manually modeled.

This constraint should only be used by advanced users as it is usually difficult to provide valid latency values.