Clock Enables - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

When used properly, clock enables can significantly reduce design power with little impact on area or maximum clock frequency. However, when clock enables are used improperly, they can lead to:

  • Increased resource utilization
  • Decreased placement density
  • Increased power
  • Reduced achievable clock frequency

In most cases, low fanout clock enables are the main contributor to the high number of control sets.