Checking for Feedback Structures in Registers - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-11-29
Version
2023.2 English

Make sure that registers do not have feedback logic, because this prevents register optimizations. In the following example, the address register drives both the RAM and the adder, which means that the register cannot be packed into a block RAM. The resulting circuit is a block RAM in which the dout register is packed into the RAM to make the RAM fully synchronous. However, the RAM does not use the output registers (DOA_REG and DOB_REG will be set to '0'), which is inefficient.

Figure 1. Check for the Presence of Feedback on Registers Around the RAM Block
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