Certain Hardware Primitive Output Pins - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

You can use the output pin of certain hardware primitives as the primary clock root, such as the output pin shown in the following figure, which does not have a timing arc from an input pin of the same primitive.

Figure 1. Clock Path Broken Due to a Missing Timing Arc

Important: No primary clock should be defined in the transitive fanout of another primary clock because this situation does not correspond to any hardware reality. It will also prevent proper timing analysis by preventing the complete clock insertion delay calculation. Any time this situation occurs, the constraints must be revisited and corrected.

The following figure shows an example in which the clock clk1 is defined in the transitive fanout of the clock clk0. The clock clk1 overrides clk0 starting at the output of BUFG1, where it is defined. Therefore, the timing analysis between REGA and REGB is not accurate because of the invalid skew computation between clk0 and clk1.

Figure 2. create_clock in the Fanout of Another Clock is Not Recommended