Balance SLR Utilization for SSI Devices - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

When targeting SSI technology devices it is important to analyze the utilization per SLR region. Overall utilization might be low, but high utilization in one SLR might lead to a congestion.

In the following figure, the overall utilization for the design is low. However, the utilization in SLR2 is high and the logic requires more routing resources than logic in the other SLRs. The logic in this area is a wide bus MUX that saturates the routing resources.

Figure 1. Utilization Analysis per SLR Region

To balance utilization, try the following:

  • Use different placer directives for spreading the design.
  • Use floorplanning constraints, such as Pblocks to keep some modules out of the highly utilized and congested SLR.