Avoiding Local Clocks - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

Local clocks are clock nets routed with regular fabric resources instead of dedicated global clocking resources. In most cases, the Vivado synthesis and Vivado logic optimization tools insert clock buffers where mandated by the architecture or for clock nets with more than 30 clock loads. Local clocks typically occur when:

  • A global clock is divided by a counter implemented with fabric logic
  • Clock gating conversion is not able to remove all LUTs from the clock path
  • Too many clock buffers are used in 7 series devices
    Note: UltraScale devices have more clock buffers than 7 series devices, and high utilization of low fanout clock buffers is usually not a concern.

In general, avoid using local clocks. Local clocks introduce several challenges to the implementation tools:

  • Unpredictable clock skew, leading to difficult timing closure
  • Increase of low to medium fanout nets that are processed with special care by the router, leading to potential routability problems
    Tip: If local clocks introduce timing QoR problems, try floorplanning the clock driver and loads to a small area using a Pblock. Use report_clock_utilization to identify the location of the local clocks, review the clock placement, and decide on how to reduce their number or impact.