In this section, you create an example design and an Intelligent Design Run (IDR).
- First, you need a project. Select Open Example
Project.
- Click → BFT and then select
Next again.
- In the next screen, ensure you are working on in a suitable writable directory, and select Next.
- For part selection, you must select xcku035-fbva900-2-e and then select .
You should now have an open project that is waiting to be synthesized.
Note: IDRs are not supported for 7 series devices. Selecting the incorrect family requires you to regenerate the project. - This lab aims to demonstrate how to add a Tcl file to an IDR. To do this, add a file to impl_1. In the Design Runs window, select impl_1.
- In the Implementation Run Properties window, select the Options tab.
- Scroll to the
opt_design
tcl.pre option and add the Tcl script<extract_dir>/Lab4/pre_opt.tcl
to the option.
Alternatively, use the following Tcl syntax:add_files -fileset utils_1 -norecurse <extract_dir>/Lab4/pre_opt.tcl set_property STEPS.OPT_DESIGN.TCL.PRE [ get_files <extract_dir>/Lab4/pre_opt.tcl -of [get_fileset utils_1] ] [get_runs impl_1]
- In the Flow Navigator, click Run Synthesis.
- The next step is to create the Intelligent Design Run. In the Design Runs window, right-click on .
If you try this step again to create an additional run, you find that the option is disabled. This is to prevent the creation of runs that would produce the same results. Runs created from the same netlist with different directives produce the same results because the IDR controls the directive, meaning that they are effectively the same.
If you have a different floorplan or speed grade, create different implementation runs. You can create one IDR from each implementation run.