Using the Vivado Integrated Logic Analyzer - 2023.2 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

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2023.2 English
  1. In the Flow Navigator, under Program and Debug, select Open Hardware Manager.

  2. The Hardware Manager window opens. Click Open Target > Open New Target.

  3. The Open New Hardware Target wizard opens. Click Next.
  4. In the Hardware Server Settings page, type the name of the server (or select Local server if the target is on the local machine) in the Connect to field. Click Next.

    Note: Depending on your connection speed, this can take about 10 to 15 seconds.
  5. If there is more than one target connected, you see multiple entries in the Select Hardware Target page. In this tutorial, there is only one target, as shown in the following figure. Click Next.

  6. In the Open Hardware Target Summary page, click Finish as shown in the following figure.

  7. Wait for the connection to the hardware to complete. The dialog in the following figure appears while hardware is connecting.

    After the connection to the hardware target is made, the Hardware window appears as in the following figure.

    Note: The Hardware tab in the Debug view shows the hardware target and XC7K325T device detected in the JTAG chain.

  8. Next, program the XC7K325T device using the previously created .bit bitstream by right-clicking the XC7K325T device and selecting Program Device as shown in the following figure.

  9. In the Program Device dialog box verify that the .bit and .ltx files are correct for the lab that you are working on and click Program to program the device as shown in the following figure.

    The file paths of the bitstream and debug probes to be programmed are different for different labs. Ensure that the relative paths are correct.
    Note: Wait for the program device operation to complete. This can take a few minutes.
  10. Ensure that an ILA core was detected in the Hardware panel of the Debug view.

  11. The Integrated Logic Analyzer dashboard opens, as shown in the following figure.