Step 3: Create DCPs for the Black Box Created in Synplify Pro - 2023.2 English - UG936

Vivado Design Suite Tutorial: Programming and Debugging (UG936)
Document ID
UG936
Release Date
2023-11-01
Version
2023.2 English
The black box, sinegen, created in the Synplify Pro project, contains the Direct Digital Synthesizer IP. You need to create a synthesized design for this block. To do this, create an RTL-type project in Vivado IDE by the following steps:
  1. Launch Vivado IDE.
  2. Click Create Project. This opens up the New Project wizard. Click Next.
  3. Under Project Name, set the project name to proj_synplify_netlist. Click Next.
  4. Under Project Type, select RTL Project. Click Next.
  5. Under Add Sources, click Add Files, navigate to the Vivado_Debug/src/lab4 folder and select the sinegen.vhd file. Set Target Language to VHDL. Ensure that Copy sources into the project box are selected. Click Next.
  6. Click Add Files, navigate to the Vivado_Debug/src/lab4 folder, and select the sine_high.xci, sine_low.xci, and sine_mid.xci files. Click Next.
  7. Under Default Parts, select Boards and select the Kintex 7 KC705 Evaluation Platform and the correct version for your hardware. Click Next.
  8. Under New Project Summary, ensure all the settings are correct. Click Finish.
  9. Once the project is created, in Vivado Flow Navigator, under the Project Manager folder, click Settings. In the dialog box, in the left panel, click Synthesis. From the pull-down menu on the right panel, set -flatten_hierarchy to none. Click OK.
  10. In Vivado IDE Flow Navigator, under Synthesis Folder, click Run Synthesis.
  11. When synthesis completes, the Synthesis Completed dialog box appears. Select Open Synthesized Design and click OK.
  12. Click File > Exit in Vivado IDE. When the OK to exit dialog box pops up, click OK.