Step 1: Opening the Example Design and Adding a Debug Core - 2023.2 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

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2023.2 English
  1. Start the Vivado IDE.

    Load the Vivado IDE by doing one of the following:

    • Double-click the Vivado IDE icon on the Windows desktop.
    • Type vivado in a command terminal.

    From the Getting Started page, click Open Example Project.

  2. In the Open Example Project dialog box, click Next.
  3. Select the CPU (Synthesized) design template, and click Next.
  4. In the Project Name dialog box, specify the following:
    • Project name: project_cpu_incremental
    • Project location: <Project_Dir>

    Click Next.

  5. In the Default Part screen, select xc7k70tfbg676-2 and click Next.
  6. The New Project Summary screen appears, displaying project details. Review these and click Finish.
  7. When the Vivado IDE opens with the default view, open the Synthesized design.
  8. In the Netlist window, select the set of signals specified in the cpuEngine hierarchy and apply the MARK_DEBUG property by right-clicking and selecting Mark Debug from the dialog.

    Alternatively, you can use the following Tcl command to set the MARK_DEBUG property on the signals specified.
    set_property mark_debug true [get_nets [list {cpuEngine/dcqmem_dat_qmem[*]}
     {cpuEngine/dcpu_dat_qmem[*]} {cpuEngine/dcqmem_adr_qmem[*]} 
    {cpuEngine/du_dsr[*]} {cpuEngine/dvr0__0[*]} {cpuEngine/du_dsr[*]} 
  9. In the Flow Navigator, click Set Up Debug to invoke the Set Up Debug wizard.

  10. When the Set Up Debug Wizard appears, click Next.

  11. When the ILA Core Options screen appears, click Next again.
  12. When the Set Up Debug Summary screen appears, ensure that one debug core is created and click Finish.
  13. Check the Debug window to ensure the u_ila_0 core is inserted into the design.

  14. Save the new debug XDC commands by selecting File > Constraints > Save or clicking the Save Constraints button.