Step 1: Creating a Project with the Vivado New Project Wizard - 2023.2 English - UG936

To create a project, use the New Project wizard to name the project, add RTL source files and constraints, and specify the target device.

1. Invoke Vivado IDE.
2. In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
3. In the Project Name page, name the new project proj_hdl_vio and provide the project location (C:/Vivado_Debug). Ensure that the Create project subdirectory is selected. Click Next.
4. In the Project Type page, specify the Type of Project to create as RTL Project. Click Next.
5. In the Add Sources page:
   1. Set Target Language to VHDL.
   2. Click Add Files.
   3. In the Add Source Files dialog box, navigate to the /src/lab3 directory.
   4. Select all VHD source files, and click OK.
   5. Verify that the files are added, and Copy Sources into Project is selected.
6. Click the “+” sign, and click Add Directories.
7. In the Add Source Directories dialog box, navigate to the /src/lab3 directory and choose the sine_high, sine_low, sine_mid, and ila_0 directories. Click Select.
8. Verify that the directories are added, and Copy sources into the project are selected. Click Next.
9. In the Add Constraints dialog box, click the “+” sign, and click Add Files.
10. Navigate to the /src/lab3 directory and select sinegen_demo_kc705.xdc. Click Next.
11. In the Default Part page, specify the xc7k325tffg900-2 platform. You can also select Boards and select Kintex 7 KC705 Evaluation Platform. Click Next.
12. Review the New Project Summary page. Verify that the data appears as expected by the previous steps. Click Finish.
    Note: It might take a moment for the project to initialize.
13. In the Sources window in Vivado IDE, expand sinegen_demo_inst_vio to see the source files for this lab.
    Note: The ila_0 core is added to the project. However, vio_0 (the VIO core) is missing.
    
    
    
14. Instantiate and configure this VIO core as follows. From the Flow Navigator, click IP Catalog, expand Debug & Verification, expand Debug, and double-click VIO. The Customize IP dialog box opens.
15. On the General Options tab, leave the Component Name as its default value of vio_0, set Input Probe Count to 1, Output Probe Count to 1, and select the Enable Input Probe Activity Detectors check box.
    
    
16. On the PROBE_IN Ports tab, set Probe Width to 4.
    
    
17. On the PROBE_OUT Ports tab, set Probe Width to 2 and Initial Value to 0x0.
    
    
18. Click OK to generate the IP. The Generate Output Products dialog box appears. Click Generate. An additional dialog box can appear, indicating an out-of-context module run is launched. If so, click OK.
    
    

    Output product generation should take less than a minute. At this point, you have finished customizing the VIO. This core is already instantiated in the top-level design.

    
    
    

    At this point, the Sources window should look as shown in the following figure.

    
    
    
19. Double-click sinegen_demo_inst.vhd in the Sources window to open it, and inspect the instantiation and port mapping of the ILA core in the HDL code.