Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

The USER_RAM_AVERAGE_ACTIVITY constraint specifies a value representing the average frequency of all UltraRAM and Block RAM on the device that can be switched (enabled/disabled). The value is used by Vivado to model power supply noise induced by RAM switching and calculate jitter for global clocks in static timing analysis.

When USER_RAM_ACTIVITY is unspecified or set to -1, Vivado performs a pessimistic estimate that will result in a pessimistic jitter value (reported as part of the clock uncertainty in static timing analysis) and ultimately results in increased difficulty for design timing closure. The pessimistic estimate performed by Vivado is deposited on the RAM_AVERAGE_ACTIVITY property.

For example, a design using 40% of the available UltraRAM and Block RAM operating at 400 MHz results in a USER_RAM_AVERAGE_ACTIVITY of 160. The value of 160 results in less jitter versus the pessimistic default value, easing design timing closure.

Architecture Support
Versal Adaptive SoCs.
Applicable Objects

Design (current_design)

<n>: Where n is an integer between -1 and 1150.


Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property USER_RAM_AVERAGE_ACTIVITY <n> [current_design]

XDC Syntax Examples:

# Use pessimistic default
set_property USER_RAM_AVERAGE_ACTIVITY -1 [current_design] 

# User determined value is 160

set_property USER_RAM_AVERAGE_ACTIVITY 160 [current_design]

# All UltraRAM/Block RAM are never enabled or disabled 
set_property USER_RAM_AVERAGE_ACTIVITY 0 [current_design]

Affected Steps

  • Timing Analysis
  • Implementation

See Also

  • Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)
  • Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)