USER_CROSSING_SLR - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

When placing design elements on stacked silicon interconnect (SSI) devices, you can use USER_SLR_ASSIGNMENT, USER_CROSSING_SLR, and USER_SLL_REG properties to manage logic partitioning, and the behavior of the Vivado placement tool. SSI devices consist of multiple super logic regions (SLRs), joined by interposer connections called super long lines (SLLs). For more information on placing and routing in and across SLRs, refer to this link in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).

USER_CROSSING_SLR is a boolean property that indicates that a net is allowed to cross an SLR boundary, or that the net should not cross the SLR boundary. The constraint can be applied to either nets or pins. If the USER_CROSSING_SLR is set to 1, the net can cross the SLR boundary through the SLL channel. When set to 0, the net should not cross the SLR boundary.

Important: A value of 0 can be used on any pin or net segment to indicate the net should not cross the boundary. A value of 1 can only be applied to single-fanout pipeline register connections.

To manage placement across SLRs, start with USER_SLR_ASSIGNMENT to assign logic to an SLR or group, add USER_CROSSING_SLR to control which net segment in the logic crosses the SLR boundary. Add USER_SLL_REG if needed.

USER_CROSSING_SLR=1 has no conflict with USER_SLR_ASSIGNMENT as it is used after the floorplanning placement phase. USER_CROSSING_SLR=0 has lower priority than USER_SLR_ASSIGNMENT USER_CROSSING_SLR has higher priority than USER_SLL_REG. When USER_CROSSING_SLR is in conflict with USER_SLL_REG, the latter property is ignored.

However, if both pins of a register with USER_SLL_REG (true) also have USER_CROSSING_SLR (true), but the source cell of Reg/D and the load cell of Reg/Q are placed in the same SLR, then both USER_SLL_REG and USER_CROSSING_SLR should be ignored.

Architecture Support
All architectures
Applicable Objects
  • Nets (get_nets)
  • Pins (get_pins)
  • Null (or “”): Indicates that the property is found on the net or pin, but that the property value has not been set to either TRUE or FALSE, or has been unset.
  • True (or 1): The net connected to the pin will be routed onto SLL channel if necessary for placement purposes.
  • False (or 0): The net connected to the pin will be routed inside an SLR.


Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property USER_CROSSING_SLR <value> [get_nets <net_name>]


  • <value> is the specified value for the property of NULL, TRUE, or FALSE.
  • <net_name> specifies the name of the net to assign the property to.

XDC Example 1:

set_property USER_CROSSING_SLR 0 [get_nets net_A]

Affected Steps

  • Place Design