USER_CLOCK_ROOT - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

Used to assign the clock driver, or root, to a specific clock region or Pblock on the target part.

The USER_CLOCK_ROOT property is intended to help manage clock skew across the device. By default, the place and route tools will automatically assign a clock root to achieve the best timing characteristics for the design. The tool assigned clock root is defined in the read-only CLOCK_ROOT property. The USER_CLOCK_ROOT property lets you manually assign the clock root.

Important: The USER_CLOCK_ROOT property can be set on a global clock net, and can only be assigned to the net segment directly driven by the global clock buffer (BUFG).

The USER_CLOCK_ROOT property is validated and used during clock resource placement, so the assignment should be made prior to placement. However, if you assign the property after placement, you will need to rerun placement to implement the clock root and affect the design.

Due to a more flexible clocking architecture, designs that target UltraScale devices and UltraScale+ devices require a two-step process for routing global clocks. First the Vivado placer assigns the routing resources required to route the global clocks from the clock source to the destination clock regions (CLOCK_ROOT or USER_CLOCK_ROOT). Next the Vivado router fills in the routing gaps on the clock nets.

The global clock routing is handled automatically during implementation. However in cases where the USER_CLOCK_ROOT property on a clock net has been changed after implementation, the Vivado tool might require the update_clock_routing command to properly reroute the clock nets.

Architecture Support
UltraScale and UltraScale+ architectures.
Applicable Objects
Global clock net (get_nets) directly connected to the output of a global clock buffer.
  • <clock_region | pblock>: Specifies as the name of a clock region on the target part, or a defined Pblock in the current design. The clock region can be specified by name or passed as a clock_region object by the get_clock_regions command. Similarly, the Pblock can be specified by name or returned by the get_pblocks command.
  • <objects>: Specified as one or more clock nets, or net segments.


Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property USER_CLOCK_ROOT <clock_region | pblock> <objects>

XDC Syntax Examples:

set_property USER_CLOCK_ROOT X1Y0 [get_nets {clk1 clk2}] 
set_property USER_CLOCK_ROOT [get_clock_regions X0Y0] [get_nets {clk1 clk2}]
Tip: The clock net can also be defined using the global clock buffer instance, or output pin, as shown in the following example:
set_property USER_CLOCK_ROOT X1Y0 [get_nets -of [get_pins bufferName/O]]

Affected Steps

  • Place Design
  • Routing