The USED_IN property is assigned to design files (.v, .vhd, .xdc, .tcl) in the Vivado Design Suite to indicate what stage in the FPGA design flow the files are used.
For example, you could use the USED_IN property to specify an XDC file for use by the Vivado synthesis tool, but not for use in implementation. You could also specify HDL source files (.v or .vhd) as USED_IN simulation, but not for use in synthesis.
Tip: The USED_IN_SYNTHESIS, USED_IN_SIMULATION, and
USED_IN_IMPLEMENTATION properties are related to the USED_IN property, and are
automatically converted by the tool to USED_IN ({synthesis, simulation,
implementation} as appropriate.
You can also use the more granular values to specify an unmanaged Tcl file to be
USED_IN opt_design or place_design, rather than
simply used in implementation.
- Architecture Support
- All architectures..
- Applicable Objects
- Files
- Values
-
- synthesis
- synthesis_post
- implementation
- simulation
- out_of_context
- opt_design
- opt_design_post
- power_opt_design
- power_opt_design_post
- place_design
- place_design_post
- phys_opt_design
- phys_opt_design_post
- route_design
- route_design_post
- write_bitstream
- write_bitstream_post
- synth_blackbox_stub
- testbench
- board
- single_language
- power_data
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property USED_IN {<value>} [get_files <files>]Where
-
<value>specifies one or more of the valid USED_IN values. -
<files>is the name or names of the files to set the USED_IN property.
XDC Syntax Example
# Designates the specified files as used in simulation set_property USED_IN {synthesis simulation} [get_files *.vhdl] -
Affected Steps
- Synthesis
- Simulation
- Implementation
- Bitstream generation