SLR - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

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2023.2 English


A Super Logic Region (SLR) is a single FPGA die slice contained in an stacked silicon interconnect (SSI) device. Stacked silicon interconnect (SSI) technology uses passive silicon interposers with microbumps and through-silicon vias (TSVs) to combine multiple FPGA die slices, referred to as super logic regions (SLRs), into a single package.

Each SLR contains the active circuitry common to most AMD FPGA devices, and are connected through super long lines (SLLs) found on the silicon interposers. Refer to this link in the UltraFast Design Methodology Guide for the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) for more information on working with SSI components.

Figure 1. SLR Objects

Related Objects

Super logic regions (SLRs) are die slices of AMD FPGA architecture or devices. As shown in the following figure, each SLR contains clock regions, tiles, sites, site pins, bels, bel pins, nodes, pips, cells, pins, I/O banks, and package pins. You can find the SLRs associated with each of these different types of objects, with a Tcl command such as the following, that returns the SLR that the specified cell is assigned to:

get_slrs -of [get_cells DataIn_pad_0_i_IBUF[3]_inst]

You can also query the clock regions, tiles, sites, or bels associated with an SLR. The following Tcl command gets I/O banks of the clock regions associated with a specific SLR:

get_iobanks -of [get_clock_regions -of [get_slrs SLR3]]


You can use the report_property command to report the properties of an SLR. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information. The properties on the SLR object include the following, with example values:

Property	Type	Read-only	Visible	Value
ARCH	string	true	true	virtex7
CHIP_TYPE	string	true	true	xc7vx1140t
CLASS	string	true	true	slr
CONFIG_ORDER_INDEX	int	true	true	0
IS_FABRIC	bool	true	true	1
IS_MASTER	bool	true	true	1
LOWER_RIGHT_CORNER	int	true	true	(0,157)
LOWER_RIGHT_X	int	true	true	0
LOWER_RIGHT_Y	int	true	true	157
MAX_SITE_INDEX	int	true	true	278381
MAX_TILE_INDEX	int	true	true	266114
MIN_SITE_INDEX	int	true	true	185588
MIN_TILE_INDEX	int	true	true	177410
NAME	string	true	true	SLR1
NUM_CHANNELS	int	true	true	220
NUM_SITES	int	true	true	92794
NUM_SLLS	int	true	true	10780
NUM_TILES	int	true	true	23169
NUM_TOP_DATA_CONNECTIONS	int	true	true	10780
SLR_INDEX	int	true	true	1
UPPER_LEFT_CORNER	int	true	true	(564,313)
UPPER_LEFT_X	int	true	true	564
UPPER_LEFT_Y	int	true	true	313

To report the properties for a specific SLR, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:

report_property -all [get_slrs <name>]

Where <name> is the name of the SLR to report.