RLOC - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

Relative Location (RLOC) constraints define the relative placement of logic elements assigned to a set, such as an H_SET, HU_SET, or U_SET.

When RLOC is present in the RTL source files, the H_SET, HU_SET, or U_SET properties get translated into a read-only RPM property on cells in the synthesized netlist. The RLOC property is preserved, but becomes a read-only property after synthesis. For more information on using these properties, and defining RPMs, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).

Tip: When building hierarchical RPMs, use synth_design -flatten_hierarchy none to ensure that the RLOC properties are retained on their intended levels of hierarchy.

You can define the placement of any element within the set relative to other elements in the set, regardless of the eventual placement of the entire group onto the target device. For example, if RLOC constraints are applied to a group of eight flip-flops organized in a column, the mapper maintains the column and moves the entire group of flip-flops as a single unit. In contrast, the LOC constraint specifies the absolute location of a design element on the target device, without reference to other design elements.

Architecture Support
All architectures.
Applicable Objects
Instances or Modules in the RTL source files
The Relative Location constraint is specified using a SLICE-based XY coordinate system.


  • m is an integer representing the X coordinate value.
  • n is an integer representing the Y coordinate value.
Tip: Because the X and Y numbers in Relative Location (RLOC) constraints define only the order and relationship between design elements, and not their absolute locations on the target device, their numbering can include negative integers.


Verilog Syntax

The RLOC property is a Verilog attribute defining the relative placement of design elements within a set specified by H_SET, HU_SET, or U_SET in the RTL source files. Place the Verilog attribute immediately before the instantiation of a logic element.

(* RLOC = "XmYn", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));

Verilog Example

The following Verilog module defines RLOC property for the shift register Flops in the ffs hierarchical module.

module inv (input a, output z);

LUT1 #(.INIT(2'h1)) lut1 (.I0(a), .O(z));

endmodule // inv

module ffs (
input	clk, input	d, output q

wire sr_0, sr_0n; wire sr_1, sr_1n; wire sr_2, sr_2n; wire sr_3, sr_3n; wire sr_4, sr_4n; wire sr_5, sr_5n; wire sr_6, sr_6n; wire sr_7, sr_7n;

wire	inr, inrn, outr;

inv i0 (sr_0, sr_0n); inv i1 (sr_1, sr_1n); inv i2 (sr_2, sr_2n); inv i3 (sr_3, sr_3n); inv i4 (sr_4, sr_4n); inv i5 (sr_5, sr_5n); inv i6 (sr_6, sr_6n); inv i7 (sr_7, sr_7n); inv i8 (inr, inrn);

(* RLOC = "X0Y0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
(* RLOC = "X0Y1" *) FD sr1 (.C(clk), .D(sr_2n), .Q(sr_1));
(* RLOC = "X0Y2" *) FD sr2 (.C(clk), .D(sr_3n), .Q(sr_2));
(* RLOC = "X0Y3" *) FD sr3 (.C(clk), .D(sr_4n), .Q(sr_3));
(* RLOC = "X0Y4" *) FD sr4 (.C(clk), .D(sr_5n), .Q(sr_4));

(* RLOC = "X0Y5" *) FD sr5 (.C(clk), .D(sr_6n), .Q(sr_5));
(* RLOC = "X0Y6" *) FD sr6 (.C(clk), .D(sr_7n), .Q(sr_6));
(* RLOC = "X0Y7" *) FD sr7 (.C(clk), .D(inrn), .Q(sr_7));
(* LOC = "SLICE_X0Y0" *) FD inq (.C(clk), .D(d), .Q(inr));
FD outq (.C(clk), .D(sr_0n), .Q(outr)); assign q = outr;
endmodule // ffs
Tip: In the preceding example, the presence of the RLOC property implies the use of the H_SET property on the FD instances in the ffs hierarchical module.

When using the modules defined in the preceding example, you will need to specify the KEEP_HIERARCHY property to instances of the ffs module to preserve the hierarchy and define the RPM in the synthesized design:

module top (
input	clk, input	d, output q

wire	c1, c2;

(* RLOC_ORIGIN = "X1Y1", KEEP_HIERARCHY = "YES" *) ffs u0 (clk, d, c1); (* RLOC_ORIGIN = "X3Y3", KEEP_HIERARCHY = "YES" *) ffs u1 (clk, c1, c2); (* RLOC_ORIGIN = "X5Y5", KEEP_HIERARCHY = "YES" *) ffs u2 (clk, c2, q);

endmodule // top
VHDL Syntax

Declare the VHDL constraint as follows:

attribute RLOC: string;

Specify the VHDL constraint as follows:

attribute RLOC of {component_name | entity_name | label_name} :
{component|entity|label} is “XmYn”;


  • {component_name | entity_name | label_name} is a choice of one design element.
  • {component | entity | label} is the instance ID of the design element.
  • XmYn defines the RLOC value for the specified design element.
XDC Syntax

The RLOC property can not be defined using XDC constraints. The RLOC property defines the relative locations of objects in a relatively placed macro (RPM), and results in read-only RPM and RLOC properties in the netlist of synthesized designs.

Tip: You can use the create_macro and update_macro commands to define macro objects in the Vivado Design Suite, that act like RPMs within the design. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information on these commands.

Affected Steps

  • Logical to Physical Mapping
  • Place Design
  • Synthesis