RAM_STYLE - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

RAM_STYLE instructs the Vivado synthesis tool on how to infer memory in the design. For more information about RAM coding styles, see HDL Coding Techniques in Vivado Design Suite User Guide: Synthesis (UG901).

By default, the tool selects the type of RAM to infer based upon heuristics that give the best results for most designs. Place this attribute on the array that is declared for the RAM, or a level of hierarchy, to direct synthesis to infer a specific style of RAM. If set on a level of hierarchy, this affects all RAM in that level of hierarchy. Nested levels of hierarchy are not affected.

This property can be set in the RTL or the XDC.

Architecture Support
All architectures.
Applicable Objects
Cells (get_cells): Apply to RAM cells.
  • block: Instructs the tool to infer Block RAM type components.
  • distributed: Instructs the tool to infer distributed LUT RAMs.
  • registers: Instructs the tool to infer registers instead of RAMs.
  • ultra: Instructs the tool to use the UltraScale+ URAM primitives.


Verilog Syntax

(* ram_style = “distributed” *) reg [data_size-1:0] myram [2**addr_size-1:0];
VHDL Syntax
attribute ram_style : string;
attribute ram_style of myram : signal is "distributed";
XDC Syntax
set_property ram_style distributed [get_cells myram]

Affected Steps

  • Synthesis