PULLUP - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English
Important: The PULLUP property has been deprecated and should be replaced by the PULLTYPE property.

PULLUP applies a weak logic High on a tri-stateable output or bidirectional port to prevent it from floating. The PULLUP property guarantees a logic High level to allow tri-stated nets to avoid floating when not being driven.

Input buffers (e.g., IBUF), 3-state output buffers (e.g., OBUFT), and bidirectional buffers (e.g., IOBUF) can have a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. This feature can be invoked by adding the PULLTYPE property with one of the following values to the port object connected to the buffer:

Note: When this property is applied, the PULLUP functionality will not be shown during RTL simulation which can create a functional difference between RTL simulation and the implemented design. This functionality can be verified using a gate-level simulation netlist or else the PULLUP UNISIM might be instantiated in the design in place of using this property in order to reflect this behavior in the RTL simulation.

For more information see the Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953) or the UltraScale Architecture Libraries Guide (UG974).

Architecture Support
All architectures.
Applicable Objects
Ports (get_ports): Apply to any top-level port.
  • TRUE|YES: Use a pullup circuit to avoid signal floating when not being driven.
  • FALSE|NO: Do not use a pullup circuit (default).


Verilog Syntax

Place the Verilog attribute immediately before the module or instantiation. Specify as follows:

VHDL Syntax

Declare the VHDL attribute as follows:

attribute pullup: string;

Specify the VHDL attribute as follows:

attribute pullup of signal_name : signal is “{YES|NO|TRUE|FALSE}”;
XDC Syntax
set_property PULLUP {TRUE|FALSE} [get_ports port_name]

Where port_name is the name of an input, output, or inout port.

XDC Syntax Example

set_property PULLUP TRUE [get_ports wbWriteOut]

Affected Steps

  • Logical to Physical Mapping