POST_CRC_FREQ - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

The Post CRC Frequency property (POST_CRC_FREQ) controls the frequency with which the configuration CRC check is performed for the current design. This feature is only supported in 7 series FPGAs. For more information refer to the 7 Series FPGAs Configuration User Guide (UG470).

Tip: Alternatively, AMD recommends use of the AMD Soft Error Mitigation (SEM) IP for all architectures. This IP automates the implementation of single event upset (SEU) detection and correction. For additional information, refer to the Soft Error Mitigation Controller LogiCORE IP Product Guide (PG036).

This property is only applicable when POST_CRC is set to ENABLE. Enabling the POST_CRC property controls the periodic comparison of a pre-computed CRC value in the bitstream with an internal CRC value computed by readback of the configuration memory cells.

The POST_CRC_FREQ defines the frequency in MHz of the readback function, with a default value of 1 MHz.

Architecture Support
7 series
Applicable Objects
Design (current_design): The current implemented design.
Specify the frequency in MHz as an integer with one of the following accepted values:
  • 1, 2, 3, 6, 13, 25, and 50
  • Default = 1 MHz


Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax
set_property POST_CRC_FREQ <VALUE> [current_design]

Where <VALUE> is one of the accepted values for the POST_CRC_FREQ property.

XDC Syntax Example

set_property POST_CRC_FREQ 50 [current_design]

Affected Steps

  • Write Bitstream
  • launch_runs