The LUT_DECOMPOSE property lets you reduce design congestion by executing LUT decomposition during logic optimization. The property can reduce interconnect density, and local routing congestion without having much effect on the design performance, but could have a larger impact on the design utilization when too many LUTs are decomposed. You must set LUT_DECOMPOSE to true on the hierarchical or leaf cells where LUT decomposition is desired.
Note: LUT6 and LUT5 cells are targeted for decomposition.
When LUT_DECOMPOSE attribute is applied on selected LUT5/LUT6s, the tool tries to
decompose them into back-to-back connected smaller LUTs whenever possible. LUTs with
timing constraints, DONT_TOUCH, SOFT_HLUTNM, HLUTNM, LUTNM will not be considered
for decomposition.
- Architecture Support
- All Architectures
- Applicable Objects
- Hierarchical or leaf (LUT5, LUT6) cells (get_cells).
- Values
- TRUE: Candidate for LUT decomposition.
Syntax
- Verilog Syntax
- Not Applicable
- VHDL Syntax
- Not Applicable
- XDC Syntax
-
set_property LUT_DECOMPOSE <TRUE|FALSE> [get_cells <cell(s)>]
Affected Steps
Logic Optimization (Opt Design)