HLUTNM - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)
Document ID
UG912
Release Date
2023-11-01
Version
2023.2 English

The HLUTNM property lets you group two specific and compatible LUT primitives to be placed into a single physical LUT by assigning the same <group_name>.

When LUT availability is low, the Vivado placer can automatically combine LUT instance pairs onto single LUTs to fit the design successfully. You can also use the DISABLED value for the HLUTNM property on specific LUTs to prevent the Vivado placer from combining them with other LUTs. This is useful, for example, to prevent LUT combining for debug ILA and VIO cores, keeping probes available for later modification in the ECO flow. Refer to this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908)] for more information on the ECO flow.

Difference Between HLUTNM and LUTNM

Tip: The HLUTNM property and the LUTNM property are similar in purpose, and should be assigned different values when used in the same level of hierarchy. The Vivado placer will combine LUTs that have the same LUTNM and HLUTNM values, or return warnings related to conflicting values.
  • Use LUTNM to group two LUT components that exist anywhere in the design, including in different levels of the hierarchy.
  • Use HLUTNM to group LUT components in a single hierarchical module, when you expect to have multiple instances of that module used in the design.
    • HLUTNM is uniquified per hierarchy.
Architecture Support

All architectures.

Applicable Objects
CLB LUT Cells (get_cells)
Values
  • <group_name>: A unique group name to pack specified LUTs into the same LUT6 site.
  • DISABLED: Prevents the placer from grouping the specified LUT with another LUT during placement.

Syntax

Verilog Syntax

Place the Verilog attribute immediately before the instantiation of a LUT. The Verilog attribute must be used in pairs in the same logical hierarchy.

(* HLUTNM = "group_name" *)

Verilog Syntax Example:

// Designates state0_inst to be placed in same LUT6 as state1_inst
// LUT5: 5-input Look-Up Table with general output (Mapped to a LUT6)
//	Virtex-7
// Xilinx HDL Language Template, version 2014.1 (* HLUTNM = "LUT_group1" *) LUT5 #(
.INIT(32'ha2a2aea2)	// Specify LUT Contents
) state0_inst (
.O(state_out[0]), // LUT general output
.I0(state_in[0]), // LUT input
.I1(state_in[1]), // LUT input
.I2(state_in[2]), // LUT input
.I3(state_in[3]), // LUT input
.I4(state_in[4])	// LUT input
);
// End of state0_inst instantiation
// LUT5: 5-input Look-Up Table with general output (Mapped to a LUT6)
//	Virtex-7
// Xilinx HDL Language Template, version 2014.1 (* HLUTNM = "LUT_group1" *) LUT5 #(
.INIT(32'h00330073)	// Specify LUT Contents
) state1_inst (
.O(state_out[1]), // LUT general output
.I0(state_in[0]), // LUT input
.I1(state_in[1]), // LUT input
.I2(state_in[2]), // LUT input
.I3(state_in[3]), // LUT input
.I4(state_in[4])	// LUT input
);
// End of state1_inst instantiation
VHDL Syntax

Declare the VHDL attribute as follows:

attribute HLUTNM : string;

For an instantiated instance, specify the VHDL attribute as follows:

attribute HLUTNM of instance_name : label is "group_name";

Where:

  • instance_name is a CLB LUT instance.
  • group_name is the name to assign to the HLUTNM property.

The VHDL attribute must be used in pairs in the same logical hierarchy.

VHDL Syntax Example:

-- Designates state0_inst to be placed in same LUT6 as state1_inst attribute HLUTNM : string;
attribute HLUTNM of state0_inst : label is "LUT_group1"; attribute HLUTNM of state1_inst : label is "LUT_group1"; begin
-- LUT5: 5-input Look-Up Table with general output (Mapped to SLICEM LUT6)
--	Virtex-7
-- Xilinx HDL Language Template, version 2014.1 state0_inst : LUT5
generic map (
INIT => X"a2a2aea2") -- Specify LUT Contents port map (
O => state_out(0),	-- LUT general output I0 => state_in(0),	-- LUT input
I1 => state_in(1), -- LUT input I2 => state_in(2), -- LUT input I3 => state_in(3), -- LUT input I4 => state_in(4)   -- LUT input
);
-- End of state0_inst instantiation
-- LUT5: 5-input Look-Up Table with general output (Mapped to SLICEM LUT6)
--	Virtex-7
-- Xilinx HDL Language Template, version 2014.1 State1_inst : LUT5
generic map (
INIT => X"00330073") -- Specify LUT Contents port map (
O => state_out(1),	-- LUT general output I0 => state_in(0),	-- LUT input
I1 => state_in(1), -- LUT input I2 => state_in(2), -- LUT input I3 => state_in(3), -- LUT input I4 => state_in(4)   -- LUT input
);
-- End of state1_inst instantiation
XDC Syntax
set_property HLUTNM <group_name> [get_cells <instance_name>]

Where

  • <group_name>: Specifies a group name for the HLUTNM property.
  • <instance_name>: Specifies the name of a CLB LUT instance.

XDC Example Syntax:

# Designates state0_inst LUT5 to be placed in same LUT6 as state1_inst 
set_property HLUTNM LUT_group1 [get_cells state0_inst]
set_property HLUTNM LUT_group1 [get_cells state1_inst]

Affected Steps

  • link_design
  • Place Design
Related reference