GATED_CLOCK - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

Use the GATED_CLOCK property to enable Vivado synthesis to perform conversion of gated clocks. Convert clock gating logic to utilize the flop enable pins when available. This optimization can eliminate logic on the clock tree and simplify the netlist.

This RTL attribute that instructs the tool about which signal in the gated logic is the clock. The attribute is placed on the signal or port that is the clock.

This attribute can only be set in the RTL.

Note: You can also use a switch in the Vivado synthesis tool that instructs the tool to attempt the conversion:
synth_design -gated_clock_conversion on
Architecture Support
All architectures
Applicable Objects
  • Clock input port
  • Clock signal
  • FALSE: Disables the gated clock conversion.
  • TRUE: Gated clock conversion occurs if the GATED_CLOCK attribute is set in the RTL code. This option gives you more control of the outcome.
  • AUTO: Gated clock conversion occurs if either of the following events are true:
    • The GATED_CLOCK property is set to TRUE
    • The Vivado synthesis can detect the gate and there is a valid clock constraint set. This option lets the tool make decisions.


Verilog Syntax
(* gated_clock = "true" *) input clk;
VHDL Syntax
entity test is port (
in1, in2 : in std_logic_vector(9 downto 0); 
en : in std_logic;
clk : in std_logic;
out1 : out std_logic_vector( 9 downto 0)); 
attribute gated_clock : string;
attribute gated_clock of clk : signal is "true"; 
end test;
XDC Syntax
Not applicable.

Affected Steps

  • Synthesis