EXTRACT_RESET - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

EXTRACT_RESET controls whether registers infer resets. Typically, the Vivado tools extract or not extract resets based on heuristics that typically benefit the most amount of designs. In cases where Vivado is not behaving in a desired way, this attribute overrides the default behavior of the tool. If there is an undesired synchronous reset going to the flip-flop, this attribute can force it to the D input logic. Conversely, if the tool is not inferring a reset that is specified in the RTL, this attribute can tell the tool to move that reset to the dedicated reset of the flop. This attribute can only be used with synchronous resets; asynchronous resets are not supported with this attribute.

This is a way for user to indicate on a granular level whether they want reset logic on control path or data path.

Architecture Support
All architectures.
Applicable Objects
The EXTRACT_RESET attribute can be placed on the cells, ports and nets.
  • TRUE (or YES): The enable will go directly go to the pin (R) of the register.
  • FALSE (or NO): The reset will not go to the reset pin (R) of the register.


Verilog Syntax
(* extract_reset = "yes" *) reg	my_reg;
VHDL Syntax
signal my_reg : std_logic; 
attribute extract_reset : string;
attribute extract_reset of my_reg: signal is "no";
XDC Syntax
set_property EXTRACT_RESET yes [get_cells my_reg]

Affected Steps

  • Synthesis