BLACK_BOX - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

The BLACK_BOX attribute is a useful debugging attribute that can turn a whole level of hierarchy off and enable synthesis to create a black box for that module or entity. When the attribute is found, even if there is valid logic for a module or entity, Vivado synthesis creates a black box for that level. This attribute can be placed on a module, entity, or component.

Important: Because this attribute affects the synthesis compiler, it can only be set in the RTL.

For more information regarding coding style for Black Boxes, refer to Black Boxes in Vivado Design Suite User Guide: Synthesis (UG901).

Architecture Support

All architectures.

Applicable Objects

Modules, entities, or components in the source RTL.


YES | TRUE: Specifies that the module or entity should be viewed as a black box and not expanded as part of the elaborated or synthesized design.

Important: To disable the black box feature, remove the BLACK_BOX attribute from the RTL module or entity. Do not simply set the attribute to NO or FALSE.


VHDL Syntax
attribute black_box	: string;
attribute black_box	of beh : architecture is "yes";
Verilog Syntax

In Verilog, the BLACK_BOX attribute on the module does not require a value. Its presence defines a black box.

(* black_box *) module test(in1, in2, clk, out1);
XDC Syntax

Not Applicable

Affected Steps

  • Synthesis