Setting AXI Master(s) Register Slicing and AXI Data FIFO - Setting AXI Master(s) Register Slicing and AXI Data FIFO - 2023.2 English

Setting AXI Master(s) Register Slicing and AXI Data FIFO - Setting AXI Master(s) Register Slicing and AXI Data FIFO - 2023.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document_ID

UG911

Release_Date

2023-11-01

Version

2023.2 English

Open the MHS file, and for each AXI Master, set the Enable Register Slice/Enable Data FIFO. To determine the correct settings, search the MHS using the information in the following table. When doing the search, replace <intf_name> with the associated BUS_INTERFACE name.

For example, the <intf_name> for BUS_INTERFACE M_AXI_MM2S would be M_AXI_MM2S,and the


               <intf_name>

for BUS_INTERFACE M_AXI_GP0 would be M_AXI_GP0.

Note:

There could be multiple AXI master interfaces per IP.
AXI masters connect to the AXI interconnect slave connection. Make the selection in the Slave Interfaces tab.

Table 1. AXI Master Interconnect Settings with Zynq Devices
Parameter	Exists	Does Not Exist
C_INTERCONNECT_<intf_name>_AR_REGISTER C_INTERCONNECT_<intf_name>_R_REGISTER C_INTERCONNECT_<intf_name>_AW_REGISTER C_INTERCONNECT_<intf_name>_W_REGISTER C_INTERCONNECT_<intf_name>_B_REGISTER	`SXX_AXI`: Enable Register Slice Auto	`SXX_AXI`: Enable Register Slice None
C_INTERCONNECT_<intf_name>_WRITE_FIFO_DEPTH C_INTERCONNECT_<intf_name>_READ_FIFO_DEPTH	Parameter = 32 `SXX_AXI`: Enable Data FIFO 32 deep Parameter = 512 `SXX_AXI`: Enable Data FIFO 512 deep	`SXX_AXI`: Enable Data FIFO None