ISE to Vivado Design Suite Migration Guide (UG911) - 2023.2 English - Explains how to migrate UCF designs from ISE™ and PlanAhead™ into AMD Vivado™ Design Suite as XDC-designs, for use in Project Mode and Non-Project Mode. Vivado tools provide reuse of all or part of existing designs, including importing projects and sources, and mapping constraints to Tcl commands. - UG911
Document ID
UG911
Release Date
2023-11-01
Version
2023.2 English
Introduction to ISE Design Suite Migration
Overview
Design Flows
Migrating ISE Design Suite Designs to Vivado Design Suite
Overview
Importing an XISE Project Navigator Project
Converting a PlanAhead Tool Project
Importing an XST Project File
Migrating Source Files
Mapping ISE Design Suite Command Scripts
Retrieving Tcl Command Information
Command Line Examples
Example 1: Mapping ISE Design Suite Commands to Vivado Design Suite Tcl Commands
ISE Design Suite Command Line
Similar Vivado Design Suite Tcl Command
Example 2: Vivado Design Suite Tcl Commands for Third-Party Synthesis (starting from EDIF)
Mapping Makefiles
Example: Mapping an ISE Design Suite Makefile to a Vivado Design Suite Makefile
Sample Makefile Used in the ISE Design Suite
Equivalent Makefile Used in the Vivado Design Suite
Associated Tcl Files for the Vivado Design Suite Makefile
run_vivado_opt.tcl
run_vivado_place_n_route.tcl
run_vivado_bitstream.tcl
Understanding the Differences in Messages
Understanding Reporting Differences
Understanding Log File Differences
Migrating UCF Constraints to XDC
Overview
Differences Between XDC and UCF Constraints
UCF to XDC Mapping
Constraint Sequence
Converting UCF to XDC in the PlanAhead Tool
TimeGROUP
Timing Constraints
Using the create_clock Tcl Command
In ISE
In the Vivado Design Suite
Clock Constraints
Period
Period Constraints with Uneven Duty Cycle
Generated Clocks Constraints
Period Constraints with LOW Keyword
Net PERIOD Constraints
OFFSET IN
BEFORE
AFTER
BEFORE an Input Port Net
BEFORE an Input Port Bus
To TIMEGROUP
FALLING/RISING Edge
LOW/HIGH Keyword
VALID Keyword
OFFSET OUT
AFTER
BEFORE
Output Net
Group of Outputs
From a TIMEGROUP
FALLING/RISING Edges
LOW Keyword
REFERENCE_PIN
From:To Constraints
Assigning Timing Group to an Area Group
EXCEPT
Between Groups
By Net
By Instance
By Pin
Specific Time Constraints
MAXSKEW
MAXDELAY
Physical Constraints
Placement-Related Constraints
AREA_GROUP
AREA_GROUP RANGE
SLICE
RAMB18
RAMB36
CLOCKREGION (1)
CLOCKREGION (2)
CLOCKREGION (3)
DSP48
BUFGCTRL
BUFHCE
BUFR
BUFIO
IOB Range
IN_FIFO
OUT_FIFO
ILOGIC
OLOGIC
LOC
IOB
SLICE (1)
SLICE (2)
RAMB18
RAMB36
DSP48
BUFGCTRL
BUFHCE
BUFR
BUFIO
KEEP_HIERARCHY
IOB
IN_FIFO
OUT_FIFO
ILOGIC
OLOGIC
IDELAY
IDELAYCTRL
BEL
A5LUT, B5LUT, C5LUT, D5LUT
A6LUT, B6LUT, C6LUT, D6LUT
AFF, BFF, CFF, DFF
A5FF, B5FF, C5FF, D5FF
F7AMUX, F7BMUX
IOB
TRUE
FALSE
FORCE
H_SET
U_SET
RLOC
RLOC_ORIGIN
RPM_GRID
USE_RLOC
RLOC_RANGE
BLKNM
HBLKNM
XBLKNM
HLUTNM
LUTNM
USE_LUTNM
CLOCK_DEDICATED_ROUTE
TRUE(1)
TRUE(2)
FALSE(1)
FALSE(2)
BACKBONE(1)
BACKBONE(2)
I/O-Related Constraints
IODELAY_GROUP
DCI_VALUE
DIFF_TERM
DRIVE
IOSTANDARD
SLEW
FAST
SLOW
PORTS
IN_TERM
OUT_TERM
IOBDELAY
BOTH
IBUF
IFD
KEEPER
PULLDOWN
PULLUP
VCCAUX_IO
Miscellaneous Net-Related Constraints
KEEP
SAVE NET FLAG
LOCK_PINS
ROUTE
Configuration-Related Constraints
CONFIG PROHIBIT
Pin site
Bank number
RAM(1)
RAM(2)
RAM(3)
RAM(4)
DSP48
SLICE
ILOGIC
OLOGIC
BUFGCTRL
BUFR
BUFIO
BUFHCE
Voltage
NONE
CONFIG DCI_CASCADE
CONFIG CONFIG_MODE
M_SERIAL
S_SERIAL
B_SCAN
B_SCAN+READBACK
M_SELECTMAP
M_SELECTMAP+READBACK
S_SELECTMAP
S_SELECTMAP+READBACK
S_SELECTMAP16
S_SELECTMAP16+READBACK
S_SELECTMAP32
S_SELECTMAP32+READBACK
SPIx1
SPIx2
SPIx4
BPI8
BPI16
CONFIG POST_CRC Commands
ENABLE
DISABLE
CONFIG POST_CRC_ACTION Commands
HALT
CONTINUE
CORRECT_AND_CONTINUE
CORRECT_AND_HALT
CONFIG POST_CRC_FREQ
CONFIG POST_CRC_INIT_FLAG
ENABLE
DISABLE
CONFIG POST_CRC_SOURCE
FIRST_READBACK
PRE_COMPUTED
DEFAULT Commands
DEFAULT FLOAT
DEFAULT KEEPER
DEFAULT PULLDOWN
DEFAULT PULLUP
Migrating Designs with Legacy IP to the Vivado Design Suite
Overview
Migrating CORE Generator IP to the Vivado Design Suite
Step 1: Migrating Design Using CORE Generator IP Sources
Step 2: Migrating IP to Latest Version
Migrating EDK IP to the Vivado Design Suite
Feature Differences between Vivado Design Suite IP and ISE CORE Generator IP
Migrating from XPS to IP Integrator
Overview
Key Feature Comparison between XPS and IP Integrator
Tips for Converting Designs from XPS to IP Integrator
IP Instantiation
Tcl Command for XPS IP Instantiation
IP Customization
Design Connectivity
Address Mapping
Clock and Resets
Interconnect Configuration
Setting up for Debug
Association of ELF Files
Migrating Zynq 7000 SoC-Based Designs
ZYNQ7 Processing System Block Automation
Connect Fabric Clocks to processing_system7 instance
Adding IP to the Base Design and Design Automation
Adding AXI Slave IPs (AXI4-Lite and AXI4) Example
Adding AXI Master IP (AXI4-Lite and AXI4) Example
Connecting Interrupts
Customizing Addresses to Match the XPS Design
Strategies
Setting AXI Master(s) Register Slicing and AXI Data FIFO
Setting AXI Slave(s) Register Slicing and AXI Data FIFO
Validating the Design
Verifying Parameters between XPS and IP Integrator Designs for AXI Masters and Slaves in a Zynq Platform Processor-Based Design
Finishing the Design
Migrating a MicroBlaze Processor-Based Design
Generating System Infrastructure (MicroBlaze, AXI_Interconnect, Clk_Wiz, Proc_Sys_Reset)
Determining MicroBlaze Interfaces/Base System Configuration
MicroBlaze Block Automation
Running MicroBlaze Block Automation
Using CLK Wiz/Proc Sys Reset
Connecting Interfaces for the Clocking Wizard
Designing with a platform board selected as the part:
Designing with a part selected:
Using AXI MIG/Proc Sys Reset
Connecting Interfaces for AXI MIG
Migrating AXI MIG
Adding MIG to the Block Diagram
Configuring AXI MIG
Connecting AXI MIG Interfaces
Adding IP to the Base Design
Adding Low Speed Peripherals (AXI4-Lite)
Adding High Speed Peripherals (AXI4)
Connecting Interrupts
Customizing Addresses to Match the XPS Design
Strategies
Setting AXI Master(s) Register Slicing and AXI Data FIFO
Setting AXI Slave(s) Register Slicing and AXI Data FIFO
Validating the Design
Verifying Parameters between XPS and IP Integrator Designs for AXI Masters and Slaves in a MicroBlaze Processor-Based Design
Finishing the Design
Migrating Pcores into a Vivado Design Suite Project
Managing Location Constraints
Migrating ISE Simulator Tcl to Vivado Simulator Tcl
Tcl Command Migration
Compiling Simulation Libraries
Migrating ISE ChipScope Logic Analyzer to Vivado Hardware Manager
Introduction
Legacy IP Core Support
ChipScope Pro Analyzer Core Compatibility
ILA and VIO Debug IP Cores
IBERT 7 Series GTH/GTP/GTX/GTZ v3.0 (or later) Debug IP Cores
Combining legacy ChipScope Pro and Vivado Debug IP Cores within a Design
Migrating Additional Command Line Tools to the Vivado IDE
Introduction
Migrating the ISE Partgen Command Line Tool
PartlistFile Contents
Package Information
ISE BitGen Command Line Tool
Speedprint Command Line Tool
ISE PROMGen Command Line Tool
ISE BSDLAnno Command Line Tool
ISE Data2MEM Command Line Tool
Migrating from compxlib to compile_simlib
Obsolete Primitives
Introduction
A
B
C
D
E
F
G
I
J
M
O
P
R
S
T
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Training Resources
Please Read: Important Legal Notices